Announcing Avery UCIe 2.0 Verification IP from Siemens EDA
Announcement:
Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s public launch of the UCIe 2.0 specification at the Future of Memory and Storage conference event in Santa Clara, California. We are ready and open for business, and are your design verification source for all things UCIe.
UCIe 2.0 Support
We are proud to be part of the UCIe ecosystem and to extend that to UCIe 2.0. Here is the statement of support we have made as part of today’s UCIe organization Press Release in support of UCIe 2.0:
“Building on our leadership in chiplets technology and strong track record of support for the standard, Siemens EDA is once again a key contributor for the newest version of UCIe technology. With our UCIe2.0 Verification IP and Compliance Test Suite solutions, Siemens continues its UCIe design verification leadership. And because version 2.0 of the UCIe standard incorporates advances that support mainstream design for test (DFT) practices, it paves the way for next-generation products capable of fully leveraging Siemens’ industry-leading Tessent software.”
Mike Ellow, CEO of Silicon Systems for Siemens EDA
Avery UCIe Expert Team:
At Siemens EDA our Avery Verification IP team have been working at the leading edge of UCIe protocol verification since its beginnings over 2 years now: we have built an impressive team of leaders and experts in the UCIe space; we have supported an equally impressive and growing list of partners and customers for our UCIe 1.1 and 1.0 Verification IP and Compliance Test Suite products.
We are working today with the industry teams who are at the bleeding edge of chiplet interconnect solutions around UCIe, providing standards based solutions, customizations, proprietary extensions to the base standards, and providing expert services from our team as well as product. We work with SiP integrators, and SiP package platform / foundry providers, and with dozens of Chiplet makers all innovating as part of this growing ecosystem. In many cases our Verification IP and Compliance Test Suite products have found bugs in interface design IP blocks and integrations, that were not found by other VIP providers We are ready to work with you on your UCIe 2.0 project!
Market Leadership:
We claim a market leadership in the UCIe Verification space, and as part of that responsibility, we have invested to ensure we have timely support for each spec evolution, so we are pleased to announce readiness of our UCIe 2.0 Verification IP – if you are at the leading edge as an adopter of UCIe, we are ready for your project and your UCIe verification challenges.
Technical deep dive Webinar on Aug 21
We invite you to attend our upcoming Webinar where we describe the challenges of design verification with UCIe 2.0 and describe how our solutions for Verification IP and Compliance Test Suites can address those challenges and provide you with Accelerated Confidence in your UCIe based chiplet design or SiP integration project. Register here.
FMS Event:
Come and visit us at Future of Memory and Storage (FMS) event this week here in Santa Clara, California, visit our booth and attend our expert presentations on UCIe and NVMe topics. Talk to our expert team about your verification needs for UCIe 2.0, PCIe Gen7, CXL 3.1, NVMe, Memory Models for LPDDR6 and HBM4, as well as hardware/software co-simulation solutions and emulation/prototyping based solutions.
See you there!
Avery Verification IP from Siemens EDA
Contact: Gordon Allan, Product Manager, Verification IP, Siemens EDA
