Verification IP: Why design teams buy instead of build

Verification IP: Why design teams buy instead of build

When we say verification IP, we mean pre-built verification solutions for standards-based peripheral interconnect interfaces and memories.
Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

Announcing Avery UCIe 2.0 Verification IP from Siemens EDA

Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s...
Siemens EDA VIP at Flash Memory Summit

Siemens EDA VIP at Flash Memory Summit

Come and see what Siemens EDA’s Verification IP experts are talking about at the Flash Memory Summit event. This annual...
PCIe® Gen6 verification - the PCI Express® generation comes of age

PCIe® Gen6 verification - the PCI Express® generation comes of age

Billions of us today – regardless of which Generation we belong to, Gen-X, Gen-Z, Millenials, Generation-Alpha – use PCI Express®...
Going With The Flow - Overview

Going With The Flow - Overview

I had the opportunity to visit some of our customers in Europe recently to talk about their verification flow challenges...
How Mature is your Design/Verification Organization?

How Mature is your Design/Verification Organization?

We had a good office discussion recently about various chip design/verification groups that my colleagues and I have been a...
Is Gate-Level Simulation Still Required Nowadays??

Is Gate-Level Simulation Still Required Nowadays??

A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,...