Verification Challenges and Solutions for Multi-Die Systems (UCIe)
Introduction
Multi-die systems accelerate the scaling of system functionality, reduce risk, and facilitate the creation of new product variants. However, these advantages come with challenges in functional verification and system analysis. To ensure thorough verification, all components in the dies must be thoroughly verified from a system-level perspective.
We are excited to announce that Prashant Dixit from Siemens’ Avery Verification IP team will present a paper on verifying UCIe designs and overcoming related hurdles at the Future of Memory and Storage Conference, August 6-8, 2024 (FMS2024), at the Santa Clara Convention Center.
To set the stage for his presentation, let’s briefly explore UCIe and its verification complexities. Universal Chiplet Interconnect Express (UCIe) is an open standard for die-to-die communication, enabling seamless integration of different chiplets into a cohesive system. Verifying a UCIe design includes mainband and sideband training, arbitration, muxing, lane repair, and lane reversal. This expands the scope of verification test plans to validate requests and responses on sideband channels from one end to the remote end, scoreboarding across power cycles, and different reset types.
Hence, the discussion will cover the following points:
- Seamless Integration of Protocol Layers
The presentation will explore how the integration of various protocol layers such as PCIe, CXL, or streaming protocols like AXI and CHI — with or without C2C — can be achieved using a common adapter and adaptable higher-layer stimulus. This approach enables the reuse of various test-related infrastructures (like regression suites and compliance test suites) of respective protocol layers over UCIe using a set of common APIs.
- Usability and Controllability
The verification solution prioritizes usability and controllability, aiding in activities like scoreboarding, error injection, and system-level analysis, including bandwidth and throughput measurement, performance monitoring, and benchmarking the design.
- Config Space Verification
The efficient utilization of a register adapter with the register model will be discussed for its role in config space verification.
- Advanced Debugging Strategies
The paper will also highlight how transaction recording and protocol-aware debug strategies can significantly reduce debug time, thereby accelerating the completion of verification activities.
Conclusion
By addressing these key aspects, Siemens’ Avery Verification IP aims to enhance the verification process for UCIe in multi-die systems, ensuring robust and reliable designs that meet the high standards of modern computing applications. We encourage you to attend the presentation at Future of Memory and Storage Conference to gain deeper insights into the challenges and solutions in this exciting field.
About the Presenter
Prashant Dixit is developing verification solutions for UCIe-based designs at Siemens EDA. He manages the Storage Verification IPs team, focusing on NVMe and NVMe over Fabrics testing solutions. Prashant holds a Master of Engineering degree in Microelectronics from BITS Pilani, completed in 2006.
We also welcome you to come to our booth (1051) to meet with our presenters and our other experts at the conference. Hope to see you there!
