It’s been about a year since rumblings began about starting up the next revision of the SystemVerilog IEEE Std 1800. There are many good arguments for and against creating another revision as I wrote about a few months ago. There are still people sticking with Verilog because lack of consistent language support. Another revision has the potential to get tools to converge on implementations where they have deviated from the standard because of deficiencies in the standard. There is also the opportunity enhance the language to improve productivity
There will be an informational kick-off meeting of the P1800 Working group for the next revision of the standard on Thursday, December 17th from 8:00 to 9:30 am Pacific time to discuss these issues. The target for completion of the P1800 standard is 2023, which will be 6 years between revisions. Please contact the P1800 secretary Michiel Ligthart for WebEx details.
The P1800 Working Group is entity-based, which means that, except for the Dec 17 informational meeting, participants or the companies they represent must be members of the IEEE Standards Association. See this link for membership details.
Look forward to meeting you there.