By Rick Fisette, Mentor Graphics Is DFT a barrier to tapeout? Time to consider going hierarchical.
By Steve Pateras, Mentor Graphics Ensure quality and reliability in automotive ICs with the newest technologies in silicon test.
By Steve Pateras, Mentor Graphics Memory BIST is evolving to meet the demands of automotive ICs.
By Beth Martin with Steve Pateras, Mentor Graphics Mentor’s novel EDT test point technology dramatically reduces ATPG pattern volume
By Ron Press, Mentor Graphics Inventing Cell-aware ATPG earned Mentor’s Friedrich Hapke the 2015 Bob Madge Innovation Award.
By Ron Press Inserting test compression logic just got a lot easier.
By Ron Press, Mentor Graphics Want to see a big reduction in pattern count compared to the best ATPG compression?
By Ron Press, Mentor Graphics Mentor’s EDT test points slash pattern count, test time and cost. But how about at-speed…
By Ron Press, Mentor Graphics Reuse block test patterns at the top level to control test time and cost with…
