By Jay Jahangiri and Wu Yang, Mentor Graphics By creating and applying scan patterns in the right order, you can…
Improve yield and failure analysis by identifying defects inside standard cells. Learn more in this new whitepaper.
By Geir Eide, Mentor Graphics Need to diagnose silicon failures faster and with more accuracy? Try the new cell-aware diagnosis…
In this video – How Tessent SiliconInsight improves the silicon bring-up flow.
By Ron Press, Mentor Graphics Why hasn’t IC test become a bottleneck in creating ever more advanced semiconductors? In this…
By Ron Press, Mentor Graphics Complete all the DFT work weeks earlier than usual by using a hierarchical test…
As IC makers move to smaller geometries and complex FinFETs, the existing fault models and test patterns are becoming less…
To control test cost, the order in which test patterns are created and applied matters…
Tessent is a finalist in the influential Elektra Awards. We love awards and think you should too.
