As part of our 3D IC podcast series, one of our experts’ talks with 3D InCites in a recent podcast.
They discuss chiplet technology with Tony Mastroianni, Advanced Packaging Solutions Director at Siemens Digital Industries Software, and Jawad Nasrullah, former co-founder and CTO of zGlue, Inc., chip designer, expertise in chiplets, microprocessors, HW/SW co-design and SerDes.
Chiplets are hardened blocks of IP of different semiconductor technology nodes that result from disaggregating or dismantling a System-on-Chip. These blocks reintegrate as a single package using high-speed interfaces, delivering better performance with less cost, higher yield, and lower power resulting in a slightly greater area than a heterogeneous integrated advanced package.
Chiplets are currently a hot topic for Intel, AMD and TSMC. However, this broadening market lacks standardized models. Therefore, the Chiplet Design Exchange was created.
In this conversation, Françoise talks to Anthony (Tony) Mastroianni of Siemens EDA and Jawad Nasrullah Palo Alto Electron, Inc. to demystify everything, especially for not being fluent in chip and package design.
You’ll get some back-story on the evolution of chiplets and the importance of standardizing chiplet models and workflows for the chiplet ecosystem. You’ll also learn about the Chiplet Design Exchange, the goal, and how you can become involved.
About our experts
Tony Mastroianni, Advanced Packaging Solutions Director at Siemens Digital Industries Software
Tony Mastroianni has more than 30 years of experience as an engineer and engineering manager in the global semiconductor industry. In recent years, he has focused significantly on advanced ASIC package design flow development (2.5/3D). He currently leads the development of Advanced Packaging Solutions for Siemens Digital Industries Software. Prior to joining Siemens, he served in engineering leadership positions at Inphi and eSilicon. He earned a bachelor’s degree in electrical engineering from Lehigh University and a master’s in electrical engineering at Rutgers University.
Jawad Nasrullah, former co-founder and CTO of zGlue, Inc., chip designer, expertise in chiplets, microprocessors, HW/SW co-design and SerDes.
Jawad Nasrullah is a chip designer with expertise in chiplets, microprocessors, HW/SW co-design, and SerDes. Previously Jawad was the co-founder and CTO of zGlue, Inc., a Silicon Valley chiplet startup that set the direction of chiplet technology and developed a number of heterogeneous integrated circuits. Jawad is now working on his next adventure, Palo Alto Electron. Jawad has been very active with the ODSA workgroup within OCP to help catalyze chiplet ecosystems. Before zGlue, Jawad has held leadership positions at Intel, Samsung, Sun Microsystems, and Transmeta. Jawad holds a Ph.D. degree in Electrical Engineering from Stanford University.
Three-dimensional integrated circuits take less space and deliver higher performance.