Sparse linear algebra (SLA) operations are essential in many applications such as data analytics, graph processing, machine learning, and scientific…
High-Level Synthesis (HLS) has never been more in demand for chip design. In fact, it could be said that the…
Power is one of the most critical design metrics today, but it still is an afterthought in far too many…
This webinar describes the Edge Machine Learning Accelerator SoC design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the…
Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in…
Many space and mil-aero applications require the use of specialized FPGAs with built-in protection from single event upsets. NanoXplore introduces…
Inferencing for Convolutional Neural Network(s) (CNNs) is notoriously compute intensive. This makes them an ideal candidate for hardware acceleration, which…
Excerpt from article: “Mentor Masterclass on ML SoC Design” I was scheduled to attend the Siemens EDA tutorial at DVCon…
