PCB Carolina 2017 – Another record breaking year!

PCB Carolina 2017 – Another record breaking year!

This year’s PCB Carolina electronics show was once again held at the McKimmon Center on November 8th at NC State…

Behind the TLA Winners: Fujitsu

Behind the TLA Winners: Fujitsu

This is the first in a series of blog posts showcasing the winning designs from the 27th Annual PCB Technology…

Create and Simulate PCB’s in One Environment

Create and Simulate PCB’s in One Environment

Have you ever been in a situation where you created a design or document, maybe even a presentation, and your…

Tips for Deciphering DDR Simulation Results

Tips for Deciphering DDR Simulation Results

So you’ve finished your simulation, and you have the results. For a DDR bus, this involves gobs of information. But…

PCB Technology Leadership Award Winner: SIENNA ECAD

PCB Technology Leadership Award Winner: SIENNA ECAD

I’d like to congratulate the two Technology Leadership Award winners who used the PADS design flow on their boards. This…

A Brief Introduction to Schematic Integrity Analysis

A Brief Introduction to Schematic Integrity Analysis

Detect critical design errors and eliminate design respins caused by schematic errors by automating the process of board-level verification. Xpedition…

Tackling Next-Generation PCB Designs

Tackling Next-Generation PCB Designs

Tackle next-generation high-density analog, RF, and digital/mixed-signal designs with advanced tools for High-Speed and RF design. Take a look inside…

Tailor Your Approach to PCB Layout

Tailor Your Approach to PCB Layout

Why fumble around with a GUI that makes you search for settings and switches? Your time is valuable! With PADS…

DDR Design: Write leveling for better DQ timing

DDR Design: Write leveling for better DQ timing

So far, we’ve gone through the basics of the DDR Bus, and discussed some of the Signal Integrity and timing requirements of…