Chalk Talk: SerDes Design

Chalk Talk: SerDes Design

Recently, I had the chance to work with Amelia Dalton, news editor at Techfocus Media, Inc., on a Chalk Talk…

Low-Power Designs Need Signal Integrity Analysis

Low-Power Designs Need Signal Integrity Analysis

Ask any signal integrity expert, what keeps you awake at night? Most will agree that it’s the question of being…

Are All Post-Layout PCB Design Rule Checkers Created the Same?

Are All Post-Layout PCB Design Rule Checkers Created the Same?

The answer is a resounding NO! To prove it, we’re giving away eight electrical DRCs that you can try for…

Don’t Forget the Basics! Always Check for T-Fork Topology.

Don’t Forget the Basics! Always Check for T-Fork Topology.

DDR memories allow the transfer of data at a higher speed than most other memory technologies. As the DDR technology…

What’s New in Xpedition – Design Verification

What’s New in Xpedition – Design Verification

In the last What’s New in Xpedition blog post, we reviewed the new Layout features available in the Xpedition VX.2…

Here’s What’s New in PADS Professional

Here’s What’s New in PADS Professional

PADS Professional VX.2.3 release is packed with new features as well as performance and quality enhancements including: Rigid-Flex Constraint manager…

Checking for Differential Impedance

Checking for Differential Impedance

One of the basic concepts of signal integrity is maintaining impedance. Whether a design will be successful or not can…

SerDes Design Part 6: JCOM, the Compliance Method for JESD204C Specification

SerDes Design Part 6: JCOM, the Compliance Method for JESD204C Specification

Continuing my blog series on SerDes design, today we’ll talk about JESD COM (JCOM), a newly developed variant of Channel…

What’s New in Xpedition – Layout

What’s New in Xpedition – Layout

In the last What’s New in Xpedition blog post, we reviewed the new FPGA-PCB Co-design features that are available in…