Eliminate Design Spins Through Early Validation in the Digital Domain

Eliminate Design Spins Through Early Validation in the Digital Domain

Increasing performance requirements, coupled with pressure to improve product quality, are driving engineering teams to consider alternatives to their current…

Optimizing Engineering Team Efficiency in the Face of Increasing Product Complexity

Optimizing Engineering Team Efficiency in the Face of Increasing Product Complexity

Engineering team efficiency is inversely related to the complexity of the designed product and size of the team. With increasing…

SerDes Design Part 7: ERL vs RL, the Move Toward More-Effective Characterization Metrics

SerDes Design Part 7: ERL vs RL, the Move Toward More-Effective Characterization Metrics

Ever heard of ERL? If not, you soon will. Effective Return Loss (ERL) is a new metric for SerDes channel…

Accelerate Development Through Digitalization of Design Data

Accelerate Development Through Digitalization of Design Data

In the rapid-fire process of complex electronics development, it’s easy to lose track of design data versions and possibly outdated…

I Have a Small PCB Design. Do I Need to Simulate for SI?

I Have a Small PCB Design. Do I Need to Simulate for SI?

The answer is YES! These days, nearly every designer deals with some degree of signal integrity constraints, both to maximize…

Is Your PCB Layout Correct by Design? Differential Phase Matching Could Be the Answer.

Is Your PCB Layout Correct by Design? Differential Phase Matching Could Be the Answer.

One of the most important benefits of HyperLynx DRC is its ability to look for niche SI-related problems that other…

PCB Tech Talk Podcast: Is Pre-Layout Schematic Verification Possible?

PCB Tech Talk Podcast: Is Pre-Layout Schematic Verification Possible?

Is design verification at the schematic level, before you take any steps into the PCB layout phase in the PCB…

PCB Tech Talk Podcast: Is Pre-Layout Schematic Verification Possible?

PCB Tech Talk Podcast: Is Pre-Layout Schematic Verification Possible?

Is design verification at the schematic level, before you take any steps into the PCB layout phase in the PCB…

Chalk Talk: Suppressing Noise from Via-to-Via Coupling

Chalk Talk: Suppressing Noise from Via-to-Via Coupling

Like Cristian Filip who recently spoke on SerDes design, I just did my first Chalk Talk with EE Journal. News…