After identifying design issues and their root cause(s), the next step is to fix them on the board and execute…
Often, either the setup or hold time margin may be very low. If setup is low while hold time is…
So you’ve finished your simulation, and you have the results. For a DDR bus, this involves gobs of information. But…
So far, we’ve gone through the basics of the DDR Bus, and discussed some of the Signal Integrity and timing requirements of…
Once we have a topology for the data and address busses in mind or have them laid out on the…
Continuing my blog series on DDR [Part 1 – Controlling DDR, Part 2 – Memory Bus Basics, Part 3 –…
So far, this blog series has discussed the stress of DDR design and introduced the DDR memory and address busses. We…
In the first blog in my series about DDR design, I talked about the stress of dealing with DDR. To…
Designing a high-speed bus can be stressful. Wide, high-speed busses, such as DRAM DDR memory busses, can be especially…well, memorable….
