Nitin Bagwath
So You’ve Found DDR Design Problems. Now What?

So You’ve Found DDR Design Problems. Now What?

December 12, 2017
After identifying design issues and their root cause(s), the next step is to fix them on the board and execute...
By Nitin Bagwath
< 1 MIN READ
Several Phenomena can Cause DDR Signals to Behave Badly

Several Phenomena can Cause DDR Signals to Behave Badly

November 30, 2017
Often, either the setup or hold time margin may be very low. If setup is low while hold time is...
By Nitin Bagwath
< 1 MIN READ
Tips for Deciphering DDR Simulation Results

Tips for Deciphering DDR Simulation Results

November 9, 2017
So you’ve finished your simulation, and you have the results. For a DDR bus, this involves gobs of information. But...
By Nitin Bagwath
< 1 MIN READ
DDR Design: Write leveling for better DQ timing

DDR Design: Write leveling for better DQ timing

October 24, 2017
So far, we’ve gone through the basics of the DDR Bus, and discussed some of the Signal Integrity and timing requirements of...
By Nitin Bagwath
< 1 MIN READ
Receiver requirements in DDR design

Receiver requirements in DDR design

October 16, 2017
Once we have a topology for the data and address busses in mind or have them laid out on the...
By Nitin Bagwath
< 1 MIN READ
What causes undesirable SI in DDR designs?

What causes undesirable SI in DDR designs?

October 10, 2017
Continuing my blog series on DDR [Part 1 – Controlling DDR, Part 2 – Memory Bus Basics, Part 3 –...
By Nitin Bagwath
< 1 MIN READ
The Back and Forth of the DDR Data Bus

The Back and Forth of the DDR Data Bus

September 13, 2017
So far, this blog series has discussed the stress of DDR design and introduced the DDR memory and address busses. We...
By Nitin Bagwath
< 1 MIN READ
Understanding the DDR memory bus

Understanding the DDR memory bus

September 6, 2017
In the first blog in my series about DDR design, I talked about the stress of dealing with DDR. To...
By Nitin Bagwath
< 1 MIN READ
Take Control of DDR Stress

Take Control of DDR Stress

August 29, 2017
Designing a high-speed bus can be stressful. Wide, high-speed busses, such as DRAM DDR memory busses, can be especially…well, memorable....
By Nitin Bagwath
< 1 MIN READ
How to Conquer the DDR Design Doldrums

How to Conquer the DDR Design Doldrums

November 7, 2016
There have been times, when designing a board, that I had an uneasy feeling in the pit of my stomach....
By Nitin Bagwath
< 1 MIN READ
Using Data Bus Inversion to Mitigate Simultaneously Switching Noise

Using Data Bus Inversion to Mitigate Simultaneously Switching Noise

June 24, 2015
This is the third post in a three part series that examines the problem of SSN and explores methods of...
By Nitin Bagwath
< 1 MIN READ
Simultaneously Switching Noise: the Effect of the Power Distribution Network

Simultaneously Switching Noise: the Effect of the Power Distribution Network

June 17, 2015
This is the second post in a three part series that will examine the problem of SSN and explore methods...
By Nitin Bagwath
< 1 MIN READ
Simultaneously Switching Noise: An Overview

Simultaneously Switching Noise: An Overview

June 2, 2015
This is the first post in a three part series that will examine the problem of SSN and explore methods...
By Nitin Bagwath
< 1 MIN READ
DDR4: Not Your Grandfather’s DDR

DDR4: Not Your Grandfather’s DDR

February 17, 2015
A long time ago, when DDR first came out, some of you may remember that it was difficult to design...
By Nitin Bagwath
< 1 MIN READ