So You’ve Found DDR Design Problems. Now What?

After identifying design issues and their root cause(s), the next step is to fix them on the board and execute a subsequent simulation.

To find an optimal fix, it’s useful to perform a set of “what-if” experiments. Rather than re-layout the board and then see whether the new layout meets SI requirements, it’s faster to examine one of the failing nets and re-test the new setup. HyperLynx® LineSim® provides an environment conducive to quickly changing parameters so that you can test a number of permutations without having to actually lay out each configuration. For example, with HyperLynx you can vary line segment length, dielectric constants of materials, and spacing between traces to find the optimal combination for your design.

Once a working solution is found, it can be laid out on the board. The newly laid out board can then be re-tested. During these “post-fix” simulations, you can save time by first simulating only the section that changed. After the local fixes have been tested adequately, you can go on to simulate the entire board/system.

Finally, once the board is manufactured, the simulated waveforms can be compared with waveforms obtained by oscilloscope measurements. It is usually impractical to measure every signal on the bus so, if a few signals measured on the oscilloscope can be validated with the measurements made by simulation, this will increase the confidence of a correct simulation setup.

One thing to keep in mind when comparing measurements with simulation is that they need to be measured at the same location. If the signal is being measured at the bottom of an IC ball, for example, this is where the simulation measurement needs to be done as well.

With a good setup and proper analysis, simulation can help decrease the overall time required to design a high-speed DDR subsystem. Learn how to guarantee margins before you build and ship boards.

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This article first appeared on the Siemens Digital Industries Software blog at