So far, this blog series has discussed the stress of DDR design and introduced the DDR memory and address busses. We will now continue with the Data/DQ bus.
The data bus, unlike the address bus, is bi-directional, shuttling signals back and forth between the DRAM and the controller. When data needs to be written to the DRAM, the controller drives the data bus. Similarly, when data needs to be read from the DRAM, the DRAM drives the data bus to send out the stored data.
There are three types of signals on the data bus: the strobe (DQS), the data (DQ), and the data mask (DM). The DQS, DQ, and DM signals are grouped into “lanes.” Depending on the type of DRAMs used, there can be four or eight DQ signals per DQS signal.
The DQS is used to synchronize the sampling of the DQ and DM signals, which are sampled on both the rising and falling edges of the strobe. On a side note, it is because of the sampling on both rising and falling edges of the strobe that the name “DDR,” or “Double Data Rate” comes into the picture.
The bandwidth of a given memory bus is measured in the amount of data that can be passed between the controller and the DRAMs in a given amount of time. To increase this bandwidth, the number of data bits, and hence the number of lanes, can be increased. For small embedded designs, there might be 8, 16, or 32 bits of DQ bits on the data bus, usually corresponding to 1, 2, or 4 lanes. Systems demanding greater bandwidth can have 64 DQ bits in parallel (or more, when including error correction bits).
When more memory is required, a common approach is to increase the capacity size of the DRAMs. However, this is limited by the technology of the DRAMs currently in production. Very dense DRAMs can be prohibitively expensive.
An alternative option is to increase the number of DQ bits and add an extra memory IC onto the extra signals. This requires allocating a greater number of pins to the controller for the new DQ bits. It also requires a larger parallel footprint on the PCB. Depending on the system, this might not be an option.
A third option is to increase the number of “ranks” in the system. This is to say that, rather than leaving the DQ signal as a point-to-point connection between the controller and one DRAM, the data signal can be shared amongst multiple DRAMs. This way, the controller can access a greater number of DRAMs without requiring a greater number of DQ pins.
With multiple ranks come new challenges. First, since the address bus is shared amongst all DRAMs, how is a given command to be assigned to a given rank? This is done by the use of “Chip Select” (CS) signals. Each rank will have its own CS allocated to the DRAMs on that rank. So a given command will be accepted by a DRAM if it also has its CS asserted; otherwise, the DRAM ignores the command.
Clearly, the back and forth signal transfer of the DDR data bus is not without its challenges! We will discuss the signal integrity effects of DDR memory, including the use of multiple loads (ranks), in our next blog.