Node Migration—What Does it Really Cost You?

Node Migration—What Does it Really Cost You?

By John Ferguson – Mentor, A Siemens Business Deciding when and how to make a process node transition is critical…

CMP Modeling: Improving Manufacturing Results during Design

CMP Modeling: Improving Manufacturing Results during Design

By Jeff Wilson and Ruben Ghulghazaryan – Mentor, A Siemens Business Accurate CMP models and simulation are crucial to both design process…

The Speed of Reliability

The Speed of Reliability

By Dina Medhat – Mentor, A Siemens Business Electrical overstress (EOS) can damage or destroy an IC. The Calibre PERC…

No Compromise: Fast, Accurate Parasitic Extraction at Advanced Nodes

No Compromise: Fast, Accurate Parasitic Extraction at Advanced Nodes

By Chris Clee – Mentor, A Siemens Business Calibre’s innovative hybrid approach to parasitic extraction can solve your PEX challenges…

In-Design Signoff DRC: Not Just a Dream

In-Design Signoff DRC: Not Just a Dream

By Srinivas Velivala – Mentor, A Siemens Business Are you a custom or analog/mixed signal (AMS) designer? How often do…

Searching for Latch-up in All the Right Places

Searching for Latch-up in All the Right Places

By Matthew Hogan – Mentor, A Siemens Business While any error in a layout could be deemed unintentional (I mean, who…

Take the Risk out of Signoff with Calibre YieldEnhancer Chip Polishing

Take the Risk out of Signoff with Calibre YieldEnhancer Chip Polishing

By Bill Graupp – Mentor, A Siemens Business Designing integrated circuits (ICs) today is a complex and high-risk endeavor…

Okay, I released my design to the fab, now what? Design to Mask – Part 2

Okay, I released my design to the fab, now what? Design to Mask – Part 2

By Minghui Fan – Mentor, a Siemens Business Managing the computational demands of today’s OPC and RET takes a dedicated…

What does physical verification need today?

What does physical verification need today?

By Juan Rey – Mentor, A Siemens Business