Lane ends—full-chip merge ahead

Lane ends—full-chip merge ahead

By James Paris – Mentor, A Siemens Business Fast layout merging during continuous build flows makes it easier to solve…

Simplify your life with Calibre RVE filters!

Simplify your life with Calibre RVE filters!

Sometimes there are simply too many choices in life. Who needs 35 flavors of juice, or 20 different hammers? Having…

Vroom! Vroom! Getting to the tapeout finish line faster…

Vroom! Vroom! Getting to the tapeout finish line faster…

By Srinivas Velivala – Mentor, A Siemens Business The Calibre RealTime Digital interface helped Qualcomm spend less time fixing DRC…

High voltage and multiple power domain designs need a little TLC (and automated VA-DRC)

High voltage and multiple power domain designs need a little TLC (and automated VA-DRC)

By Sherif Hany – Mentor, A Siemens Business High-voltage and multiple power domain applications demand high reliability. Calibre PERC enhanced…

What is critical area analysis and why should I care?

What is critical area analysis and why should I care?

By Simon Favre – Mentor, A Siemens Business Have you ever wondered what critical area analysis can do for you?…

Back to the future (or how to solve problems before they exist)

Back to the future (or how to solve problems before they exist)

By Ruben Ghulgazaryan, JinHee Kim, Jeff Wilson – Mentor, A Siemens Business Foundries and design companies working together in a…

Whither goest 3D-IC?

Whither goest 3D-IC?

By John Ferguson – Mentor, A Siemens Business Assembly-level design kits may be a critical factor in the emergence of…

When is a DRC error not an error?

When is a DRC error not an error?

By John Ferguson – Mentor, A Siemens Business Error waivers are the dark matter of IC verification—they cancel out DRC…

The best things come in small packages

The best things come in small packages

By John Ferguson – Mentor, A Siemens Business Do you know what the three challenges of HDAP design are? Are…