Calibre IC Manufacturing in 2025: The year’s biggest news

By Calibre IC Design & Manufacturing

As we launch into an exciting 2026 for the Siemens Calibre IC Manufacturing group, let’s take a quick tour of the highlights of 2025. We introduced or expanded breakthrough solutions in computational metrology and accelerated the entire Calibre IC Manufacturing flow with machine learning (ML) and artificial intelligence (AI).

New computational metrology/inspection review tools

In 2025, the Calibre IC Manufacturing group proudly launched its new computational metrology/inspection review tools (MIR). This release includes the Siemens Machine-Learning ADC (automatic defect classification), a powerful tool that performs ML-based automatic defect classification, significantly enhancing the accuracy and performance of mask inspection. We also introduced the Siemens ART (actinic review tool) Simulator to accelerate mask defect dispositioning. This innovation directly improves the efficiency and turnaround time (TAT) of mask defect review processes, a critical step in semiconductor manufacturing.

Alt text: An image showing components of the Siemens computational metrology/inspection review technologies. The top of the image features icons for capabilities like care-area generation, image quality assessment, SEM2Layout alignment, image distortion correction, contour extraction , machine learning ADC and automation. The lower part of the image shows flows for hotspot discovery and contour-based OPC modeling. — Figure 1. Siemens computation metrology/inspection review (MIR) key capabilities.

Expanded monotonic machine learning technology

The year 2025 marked a significant milestone for monotonic machine learning technology (MML) within Siemens. The latest Calibre MML production release brought this cutting-edge technology to the forefront, enabling accelerated semiconductor innovation.

The impact of this technology was recognized through an invited talk at the prestigious IWAPS conference, highlighting its growing influence in the industry.

An image showing the process begins by selecting unique patterns to create training data. The training patterns are then processed through Calibre pxOPC. Two separate MML models are trained using the ILT training masks. One is for SRAF generation and the other is for main feature prediction. The output initial mask undergoes further optimization before the final mask is produced. — Figure 2. MML’s ML/AI driven mask synthesis flow applies inverse lithography technology with rapid data-driven predictions.

You will hear more about this technology in 2026, starting with our presentation of MML for curvilinear OPC retargeting at the SPIE Advanced Lithography + Patterning symposiums on 25 February, 2026.

Read more about our 2025 SPIE activities in this blog: Siemens shines at the 2025 SPIE Advanced Lithography + Patterning Symposium

AI/ML is everywhere in Calibre IC Manufacturing

AI and ML have become pervasive within the Calibre IC Manufacturing tools, and 2025 saw a consolidation of these advancements. We published a comprehensive technical paper summarizing the extensive AI/ML capabilities: Read AI and ML in Calibre IC Manufacturing: the intelligent solutions driving innovation.

An overview of the Calibre ML model-based litho hotspot detection solution, highlighting its deep learning foundation, high prediction accuracy, and significant runtime improvements. — Figure 3. The Calibre ML model-based litho hotspot detection solution offers fast and accurate hotspot CD prediction.

At the 2025 TSMC OIP, we demonstrated the practical application and benefits of these integrated AI/ML solutions in real-world manufacturing scenarios. The work was performed in collaboration with AMD and presented jointly.

An slide showing the flow for feature-based defect prediction with the Siemens AI platform. Features collected from the design are used to train an AI model, which then performs full-chip analytics. — Figure 4. During the TSMC-OIP presentation, Siemens and AMD described a feature-based defect prediction flow with the Siemens AI platform.

Learn more about AI in Calibre in this EETimes podcast: Calibre directions in artificial intelligence

New innovations supporting advanced EUV and high-NA EUV

We continued to drive innovation in advanced EUV and high-NA EUV technologies in 2025. A significant achievement was the Siemens-imec collaboration, which successfully reduced stochastic failures in EUV lithography by orders of magnitude, validated through rigorous wafer-level experimental testing. You can read all about it in this blog post, Siemens-imec collaboration reduces stochastic failures in EUV lithography by orders of magnitude in wafer-level experimental validation.

Panels showing the performance of different OPC methods for high-NA EUV. — Figure 5. (a) Representative SEM images showing bridging defects for NOM-OPC, PW-OPC and ST-OPC in both SRAM and random logic layouts. (b) Missing and bridging probabilities for the three OPC approaches. (c) Exposure latitude (EL) vs. depth of focus (DOF) maps for the three OPC strategies in random logic designs.

We also focused on enhancing EUV lithography resolution at high numerical aperture, pushing the boundaries of what’s possible. In a paper presented at SPIE Advanced Lithography 2025, we explored a novel approach to enhancing resolution and depth of focus for EUV lithography under high-NA conditions. The key to our solution lies in the use of aperiodic multilayer masks, which offer significant advantages over conventional periodic multilayer designs. Read a summary in our blog, Enhancing EUV lithography resolution at high numerical aperture.

We delivered an invited talk on high-NA stitching at the 2025 SPIE Photomask Technology + Extreme Ultraviolet Lithography (BACUS) conference. The paper, presented jointly with imec and KLA was demonstrated collaborative advancements in this critical field.

Scanning electron microscope images of bottom mask and top mask showing shapes. Wafer data showing a defect — Figure 6. Initial experimental results of horizontal pitch 28 nm metal design stitching using 0.33NA scanner.

Learn more about the Calibre EUV solutions.

Accelerating lithography with GPUs

Graphics processing units (GPUs) are rapidly transforming the landscape of lithography, and in 2025, the Calibre IC Manufacturing group was at the forefront of this acceleration. We presented a poster at the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC25), Massively Parallel GPU Rasterizer for Next-Generation Computational Lithography, detailing the massive parallel GPU rasterizer developed for next-generation computational lithography.

The group’s contributions were also highlighted at the 2025 BACUS conference, where Danping Peng, VP of Engineering for Calibre, delivered an invited talk on model calibration on GPU and full-chip ILT on GPUs, demonstrating the power of GPU acceleration. You can watch the presentation, Mask correction to silicon: a holistic approach, on the SPIE digital library.

Further solidifying our leadership, we gave a presentation at the 2025 IEEE ACM conference focused on GPU-optimized ILT for full-chip implementation, underscoring the practical benefits of this technology.