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Connect test module with interface to design with individual ports

SystemVerilog: What is a Virtual Interface?

August 21, 2022

When I learned the SystemVerilog verification features, one concept had me baffled – virtual interfaces. What are these and why…

By Chris Spear
3 MIN READ

The UVM Config DB and Scope

November 2, 2020

Introduction With any large software project, you need to share information and control across widely separated blocks. In the bad…

By Chris Spear
3 MIN READ
OVM Extensions for Testbench Reuse

OVM Extensions for Testbench Reuse

May 4, 2010

Download OVM Configuration and Virtual Interface Extensions from OVMWorld.org Creating configurable testbench elements is critical for reuse. If you write…

By Dennis Brophy
2 MIN READ