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Implicit handle: this

SystemVerilog: Implicit handles

September 6, 2022

Introduction In the last blog post [SC(SECL1] Farmer Ted asked you to keep track of his animals and you wrote some…

By Chris Spear
4 MIN READ
Parking lot with an Automobile and Pickup, plus class variables

Class Variables and $cast

August 5, 2021

Introduction My previous post showed how SystemVerilog class variables can refer to base and derived objects. This post shows you…

By Chris Spear
4 MIN READ
Base and derived classes and their handles

Class Variables and Assignments in SystemVerilog

July 12, 2021

Introduction Good OOP style says you should start your project with a common base class (or several). When you want…

By Chris Spear
3 MIN READ

Get Your Bits Together

June 30, 2020

After my last webinar on SystemVerilog arrays, I received several questions on the differences between arrays and structures, plus how…

By Chris Spear
< 1 MIN READ
UVM Configuration DB Guidelines

UVM Configuration DB Guidelines

May 7, 2020

Introduction My previous blog posts were on static and parameterized classes to get you ready for the big game –…

By Chris Spear
3 MIN READ
SystemVerilog Static Methods

SystemVerilog Static Methods

April 29, 2020

Introduction In my last post, you learned how to create a class with a static property. This variable acts like…

By Chris Spear
2 MIN READ
SystemVerilog Classes with Static Properties

SystemVerilog Classes with Static Properties

April 21, 2020

Introduction One of the advantages of creating your testbenches with Object Oriented Programming, as opposed to traditional procedural programming, is…

By Chris Spear
2 MIN READ