As I mentioned in my last UVM post, UVM allows engineers to create modular, reusable, randomized self-checking testbenches. In that…
It’s axiomatic that digital circuitry must initialize properly before it’s used. Once upon a time, verifying a design’s reset signaling…
With ISO 26262 getting so much attention it is little wonder that ISO terms like Qualification and Tool Confidence Level…
Living on the cutting edge, as I do, I’ve been focusing most of my attention recently on the problem of…
Join us at the 53rd Design Automation Conference DAC is always a time of jam-packed activity with multiple events that…
A few weeks ago I had the honor of presenting a paper related to my prior Verification Horizons blog posts…
Just over a decade ago, Mentor Graphics had initiated a technology forum in India called the ‘EDA Tech Forum’, this…
Having been deeply involved with Universal Verification Methodology (UVM) from its inception, and before that, with OVM from its secret-meetings-in-a-hidden-hotel-room…
Using SystemVerilog to model RTL behavior in a pinch or anytime A couple weeks ago, sitting here in California on…
