Towards UVM Register Package Interoperability

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package

As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for both eventual users of the standard as well as for many EDA, IP and VIP companies that don’t participate directly in the development activities but whom could benefit from planning for tool and IP interoperability.  As the standard nears completion, it is important for other EDA and IP companies to know how they might collaborate with others in support of the pending standard.

The 23rd Synopsys EDA Interoperability Forum offers EDA and IP companies and others who will integrate the use of tools and Verification IP from several vendors a first look at the new UVM 1.0 Register Package.    The Forum’s 3:15 p.m. – 4:15 p.m. session will focus on Verification and UVM Register Package interoperability.

Mark Glasser, Methodology Architect at Mentor Graphics, will share the presentation time with a couple other presenters.  His presentation is “Building Register Verification Environment in UVM.” We encourage those who can make it to the event and have the time on October 21st to attend to do so.  Mark and other experts will be able to share their UVM development experiences and offer key insight into the newer UVM 1.0 Register Package features.

The event is free of charge, but registration is required to attend this session and any others at the Forum.  Forum details are:

Date: 21 October 2010
Time: 9:30 a.m. – 4:30 p.m.
Location: Oracle Conference Center at Agnews Historic Park, Santa Clara, CA 95054 USA
Forum Website: http://bit.ly/ccvrAk