Accellera Approves Portable Stimulus Standard – and more…
Portable Stimulus Takes Center Stage at 2018 Design Automation Conference
Accellera Systems Initiative technical teams have been busy the past year creating new standards and revising those in use. During the 2018 Design Automation Conference, the newest standard from Accellera was approve by its Board of Directors. The Portable Test and Stimulus (PSS) standard was approved to define a specification to create a single representation of stimulus and test scenarios usable by a wide variety of users across many levels of integration under different configurations. This standard will help scenarios run across execution platforms from simulation, emulation, FPGA prototyping and post-silicon debug.
There are resources online to help learn more about how you can use Accellera’s new Portable Stimulus Standard.
- Accellera Portable Stimulus Standard: Download here.
- Accellera DVCon U.S. 2018 Tutorial: Available here.
- Verification Academy PSS Basics Course: Available here.
- Verification Academy DAC 2018 Booth Presentations:
Additional Accellera Standards Updated
SystemC CCI
New SystemC Configuration, Control & Inspection (CCI) 1.0 standard was recently approved by the Accellera Board of Directors as well. Users can now use complaint tools’ configuration capabilities with any model using a complaint configuration library. The CCI features have been designed to allow existing model configuration solutions to achieve compliance through a bridge to avoid the necessity to update models and assist in an easy migration to the new standard. The new standard can be downloaded here.
UVM
New UVM Reference Implementation has been released. The Accellera UVM Working Group has release the UVM 2017 0.9 reference implementation. The reference implementation is available as a SystemVerilog class library and is fully compatible with IEEE Std. 1800.2™-2017. You can download the reference implementation here.
SystemVerilog
The IEEE completed its update of the SystemVerilog standard a year earlier and is a good companion to the updated UVM standard. Accellera has worked with the IEEE to make this standard available fee-free to the industry as well. You can find a copy of the IEEE Std. 1800™-2017 standard here.
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Where we can find what has been updated ?
Thanks,
Jamal
I am talking about UVM and System Verilog especially 🙂
Jamal, The differences for this version of UVM are covered in an update video and presentation by Accellera. You can find information to register to access the video and presentation at the Accellera UVM Resources area found here: http://www.accellera.org/community/uvm. You will want to register for “Introducing IEEE 1800.2 – The Next Step for UVM” from DVCon U.S. 2017.
You will find that the video will discuss these changes:
1. APIs were dropped
–Non-user APIs – only used by the BCL, not by end users
– Non-standard APIs – example or reference APIs, but not needed for standardization
– Examples: DAP, uvm_comparator, uvm_utils, etc…
2. New APIs were added
– New accessors
– Extendibility – things were added to allow debug to attach to them, or to extend functionality that was previously unavailable
– Examples: uvm_init, uvm_runtest_callback, etc.
3. Minor TLM cleanup – renamed as UVM to avoid scoping issues
4. Register improvements
5. “User Guide” material removed. It’s not standard-worthy.
6. Overall upgrade to remove ambiguities and clarify the specification
Many Thanks Dennis !