Join us at DVCon for a panel on Generative AI
It’s that time of year again, and I couldn’t be more excited for the 2024 Design & Verification Conference & Exhibition (DVCon), the leading conference for electronic systems and integrated circuits design and verification. This year, I have the privilege of moderating a panel titled: ‘When Will We Be Able to Say, “EDA-GPT, Verify my ASIC”?‘.
Our panel features a lineup of distinguished experts:
- Erik Berg, Principal SoC Verification Engineer, Microsoft
- Mark Ren, Director of Design and Automation Research, NVIDIA
- Daniel Schostak, Verification Architect & Fellow, ARM
- Dan Yu, AI/ML Solutions Manager, Siemens EDA
The topic at hand is of immense importance. According to Goldman Sachs, generative AI could impact up to 25% of jobs in the US and a staggering 300 million jobs globally. As contributors to the semiconductor industry, we find ourselves both driving and being impacted by this transformative trend. While AI and machine learning have already improved verification processes, the emergence of Generative AI, particularly Large Language Models (LLMs), opens up new avenues for enhancing verification productivity through acceleration, automation, and increased accuracy. However, the crucial question remains – can these promises become reality?
Many verification teams have started integrating LLMs into their workflows or are planning to do so. Yet, concerns about data copyright, privacy, potential job role impact persist. This panel is an opportunity for participants to share and discuss their perspectives, experiences, insights, and concerns regarding the role of generative AI in verification. Through this discussion, the panel aims to provide the audience with a glimpse into the future of verification, driven by LLMs, which is fast approaching.
Make sure to mark your calendar for Wednesday March 5th at 8am PDT, and come prepared with plenty of questions.
For a comprehensive list of all Siemens activities at this year’s conference, visit here.
