Whether you’re attending the Virtual DAC this week or not, I am happy to share with you that the latest issue of our Verification Horizons newsletter is out. For those of you relying on home delivery of food, meals and/or anything else, consider this our home delivery service for your Functional Verification needs:
- Formal Is The ‘New Normal’ – Deploy These FV Apps In Your Next Project from VerifWorks and CVC: If you’ve never used a formal tool before, this will give you a good overview of several Questa® Formal Apps and how best to apply them in your verification flow. I particularly like the differentiation the authors make between Specification-Driven and Implementation-Driven formal verification applications.
- Understanding the SVA Engine Using the Fork-Join Model by our long-term contributor Ben Cohen: a detailed analysis of how multi-threaded assertions actually work by modeling them as fork-joined SystemVerilog tasks.
- Bridging the Portability gap for UVM SPI VIP Core reuse from IP to Sub System and SoC using Portable Stimulus from Silicon Interfaces: shows how the new Portable Stimulus Standard can be used to create UVM sequences for a VIP Core that can be reused in multiple contexts.
- PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Application from PLDA: a great overview of the PCIe protocol and the operational modes of Mentor’s Questa® VIP PCIe component. With that understanding, the article provides a nice case study of PLDA’s experience in using the QVIP component to verify their own scalable PCIe controller soft IP component.
- Extending SoC Design Verification Methods for RISC-V Processor DV from Imperas Software: With RISC-V cores now available from multiple vendors as well as in-house designs, including the ability to customize the instruction set, the ability to ensure that your core – the heart of your entire system – functions correctly becomes paramount. The article lays out a few verification flows that can be used to do just that. As an added bonus, this one includes a video presentation of the article!
- Addressing VHDL Verification Challenges with OSVVM from Jim Lewis of SynthWorks Design: Highlights how the Open-Source VHDL Verification Methodology brings some of the capabilities availbale in SystemVerilog, like constrained-random stimulus and functional coverage, to the VHDL community.
- “Effective Verification Method of Safety Mechanism Compliant with ISO 26262 from Verification Technology: The ability to build safety mechanisms into the design to avoid catastrophic failures is critical, as is verifying that the safety mechanisms actually function correctly to ensure that the design can recover gracefully from single-point or latent hardware failures.
We here at Mentor will continue to bring you great Verification information, whether through Verification Horizons or online at the Verification Academy or our many webinars. There’s also lots of great Mentor contributions to Virtual DAC this year, so be sure to check us out.