Video: Reducing test pattern count with testpoints

At the 2023 European User2User conference, Sanmati Jain, DFT engineer at Qualcomm, describes how they achieved pattern count reduction through the efficient selection and sharing of testpoints. Test-point insertion is a DFT technique for reducing ATPG pattern count and improving test coverage. This is achieved by identifying hard to control or observe nodes in the design and intercepting with additional testpoint circuitry, which includes combinatorial gates and control, observe flops. To reduce area impact, multiple testpoints can share common control, observe flops.

In this presentation, Jain presents a case study where Tessent tools augment Qualcomm’s inhouse automation flows to achieve significant pattern reduction in range of 30%. This involves solutions to identify design hierarchies on which ATPG tool finds it difficult to generate efficient patterns. This information is used to guide the tools to focus the testpoint identification on target hierarchies. He also discusses optimal test point selection and sharing strategies to yield better results.

The presentation was recorded and is now available for anyone to view.