Revolutionizing semiconductors with 3D IC and chiplet technology

Each Industrial Revolution resulted in advancements that propelled humans forward into a seemingly different world. The first in 1784 was steam power. The second in 1870 was electricity. The third world-changing event happened in the 1960s, the computer. Now, we are living, witnessing, and enjoying the benefits provided by the fourth Industrial Revolution, Industry 4.0. With novel technologies like artificial intelligence (AI), 5G, and the internet of things (IoT), manufacturing is smarter and customer relationships are stronger.

Paving the way for advanced semiconductor designs with 3D IC and chiplet technology

The challenge is that new advancements exceed the physicality and needed power of the current monolithic chip, causing System-on-a-Chip (SoC) manufacturers to struggle with difficulties like higher cost, lower yield and restricted reticle size.

To overcome the limitations of traditional monolithic SoCs, advanced designs require adopting alternative solutions: a three-dimensional integrated circuit (3D IC). Benefits of using chiplets and 3D IC include:

• Avoiding die-size reticle restrictions
• Providing quicker signal throughput using less power
• Reducing latency by stacking memory chips on top of accessible logic
• Integrating heterogeneous silicon process technologies

But, before designers can reap 3D IC benefits to gain a competitive advantage, they must overcome formidable technological and organizational obstacles.

Understanding the basics of chiplet-based design and the advantages of using chiplets in 3D IC

To handle the rising cost of producing large dies and the physical limitations of reticle size, many leaders in the semiconductor industry are disaggregating the monolithic SoC into smaller process nodes, chiplets.

“Chiplets are fully manufactured, solid IP building blocks that perform specific, focused tasks.”¹ They have considerable chiplet-to-chiplet high performance interfaces that necessitate a close proximity to reduce energy usage and maximize data bandwidth performance. One way to conceptualize a chiplet is as a bare die that has been specifically created and optimized for use in conjunction with other chiplets contained within a package.

When used in a 3D IC, chiplets are stacked and connected, functioning as a single device that will improve performance, use less energy and require only slightly more space than a traditional two-dimensional system.

There are currently two methods for chiplet-based design.

1. Processor disaggregation happens when a complicated CPU, GPU, or AI processor is broken into plug-and-play modules that are reassembled and coupled by a silicon interposer or bridges.
2. General purpose chiplet involves using general-purpose, building-block chiplets that are constructed, aggregated, and integrated using custom application-specific integrated circuits (ASICs). A general purpose chiplet has broad appeal with its potential to provide a plug and play methodology and, also, the opportunity to scale the functionality and capabilities limited by the reticle size restrictions inherent in a monolithic SoC. However, for successful implementation, chiplet providers must provide the pertinent chiplet-related design-in intellectual property (IP), which ideally would be presented in a standardized chiplet design kit.

Chiplets and their use in 3D IC is extremely valuable. Chiplets can combine technologies that would never be used in an ASIC. Chiplets coupled in a 3D IC design can optimize process node functionalities, reduce energy consumption and attain a better overall form factor for the end product.

Heterogeneous and homogeneous integration expand possibilities. Manufacturers could choose from several different integration technology platforms that each offer their own set of advantages in terms of price, size, performance, and power consumption. However, for plug-and-play where a designer can select from an array of vendors and be confident the chips will function together, standardization of interfaces, protocols, chiplet models, and design and test flows will need to become widely accepted among chiplet manufacturers.

The future of semiconductors: Moving from monolithic SoCs to chiplet-based design

For years, IC manufacturers scaled the chip to create the necessary power and capacity to meet consumer demands, adding additional transistors to an SoC at every additional node. But, we know we’re approaching physical limits of what is possible, commonly referred to as needing “More than Moore.”

But, adopting a chiplet methodology in 3D IC design requires change from multiple perspectives with the most prominent being design.

1. Using an array of heterogeneous chiplets requires a vast, dispersed power supply network and several high-speed, high bandwidth, low latency data links.
2. Designers must consider the unique complexities of heat dissipation and thermal interaction.
3. 3D IC designers must also address price, quantity, production lead time and capacity, in addition to power delivery and performance.

Teams must also answer other design-related questions. Is inclusion of a silicon interposer the best option? Should embedded bridges be employed in an organic or redistribution layer (RDL) substrate? Can an RDL substrate such as FOWLP meet performance and power supply objectives on its own?

The shift to chiplet-based design really impacts the entire process from supply to manufacturing.

The importance of early planning and predictive analysis in 3D IC assembly

When compared to their 2D counterparts, 3D ICs offer the opportunity for vastly higher integration per unit area. While this trait is appealing for many applications, it introduces new complexities. Designing heterogeneous chiplets makes early planning and predictive analysis of the complete package assembly mandatory. Two initial focus areas are thermal and power delivery.

• Thermal analysis can begin by investigating connectivity structures and material options before physical planning starts. Using heterogeneous multi-chiplet and multi-substrate packages often introduces new connectivity structures. These can cause unexpected device performance and reliability problems related to heat dissipation and thermal-induced stresses. Early planning will prevent late-stage changes and even late-stage failures.
• Predictive power delivery analysis can occur early in the planning process before the detailed layout starts. Power delivery analysis can begin with placed chiplets and their known power consumption information.

Advantages of concurrent design for chiplet co-optimization

In addition to thermal and power delivery, other challenges chiplet-based design brings is how to develop and co-optimize the interposer, package and chiplets asynchronously.

One outmoded strategy is to wait until the chiplet floorplan and bump matrix are finalized before proceeding with planning. This serial approach delays planning and limits the possibility of co-optimization of the chiplets’ external interfaces and their assignment to the carrier substrate.

To avoid a serial methodology, teams can adopt a heterogeneous hierarchical planning strategy for the parallel creation and refinement of chiplets. A hierarchical method considers that a chiplet, even as a subset of general-purpose SoC functionalities, is still designed separately with each piece likely designed by a different team on a separate timeline.

When using a heterogeneous approach, the package team does not need to wait for the bump array to be fully designed before planning the package floorplan and connectivity. The process of package planning can begin even if the chiplet design has not yet begun. The visibility and decision disclosure between disciplines allows for greater flexibility. Co-optimization is not limited, there will be no surprises and the finished 3D IC or electronic device will be superior to what came before.

Learn how to bring heterogeneous integration-based chiplet design to your organization

Workflow adoption focus areas provide immediate heterogeneous integration capability benefits while establishing a managed methodology adoption and migration process that minimizes disruption, risk and cost. The five key workflows that span several interlinked domain areas include:

1. Architecture definition
2. Design activities (including planning, prototyping, system technology co-optimization, and detailed physical implementation of the substrates)
3. Multi-physics analysis
4. Device-level test
5. Manufacturing

Download this whitepaper to learn about bringing heterogeneous integration-based chiplet design within reach of the mainstream.

¹Keith Felton, Anthony Mastroianni, Kevin Rinebold and Per Viklund, Heterogeneous chiplet design and integration (white paper), Siemens 2021