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Mentor at DVCon 2019

Mentor at DVCon 2019

Mentor, a Siemens Business will have experts presenting conference papers and posters, as well as hosting a luncheon, panel, workshop,…

Article Roundup: Generative Design for Automotive Electrical Systems, Emulation for AI, Data Prep & Testing for Big PCBs & Taming Concurrency

Article Roundup: Generative Design for Automotive Electrical Systems, Emulation for AI, Data Prep & Testing for Big PCBs & Taming Concurrency

Applying Generative Design to Automotive Electrical Systems Emulation for AI: Part One Emulation for AI: Part Two Mentor and Seica…

Article Roundup: The Self-Driving Future, Using HLS for AI Processor IP, a New Approach to Resistance Extraction, DC-DC Buck Converter Design & Design Patterns in SystemVerilog OOP

Article Roundup: The Self-Driving Future, Using HLS for AI Processor IP, a New Approach to Resistance Extraction, DC-DC Buck Converter Design & Design Patterns in SystemVerilog OOP

Will Cowboys Or Collaborators Shape The Self-Driving Future? Specialized AI Processor IP Design with HLS A New Approach To Resistance…

Article Roundup: EDA & IP Growth, HLS SLEC, Model-Based Hinting at Sub-20nm, an Integrated PCB Verification Platform & Software approaches to Hardware Verification

Article Roundup: EDA & IP Growth, HLS SLEC, Model-Based Hinting at Sub-20nm, an Integrated PCB Verification Platform & Software approaches to Hardware Verification

EDA, IP Show Strong Growth Sequential Equivalency Checks in HLS Enhanced model-based hinting may be the edge you need below…

Article Roundup: Chip Industry Transition, DFT & Safety Emulation Apps, CMP Simulation, PSS-DSL & Correlating Rule-Based & Field Solver Parasitic Extraction Results

Article Roundup: Chip Industry Transition, DFT & Safety Emulation Apps, CMP Simulation, PSS-DSL & Correlating Rule-Based & Field Solver Parasitic Extraction Results

Chip Industry In Rapid Transition Twin DFT and Mission-Critical Safety Apps for Pre-Silicon Design Verification Tackling Manufacturing Errors Early with…

Article Roundup: Mentor on life with Siemens, What Makes a Chip Successful, Computer Vision, SoC Library Characterization & Debug Tops Verification Tasks

Article Roundup: Mentor on life with Siemens, What Makes a Chip Successful, Computer Vision, SoC Library Characterization & Debug Tops Verification Tasks

Mentor Graphics on life with Siemens (pt1) & Mentor Graphics on life with Siemens (pt2) What Makes A Chip Design…

Article Roundup: SystemVerilog Classes, Mixed-Signal Verification, Production Line Simulations, Advanced Packaging & Embedded Program Structure

Article Roundup: SystemVerilog Classes, Mixed-Signal Verification, Production Line Simulations, Advanced Packaging & Embedded Program Structure

A short course on SystemVerilog classes for UVM verification Cracking The Mixed-Signal Verification Code Automation Simulations for Efficient, Turnkey Solutions…

Article Roundup: Santa’s Autonomous Sleigh, Improving IC Yield Ramp, Silicon Photonics, Custom IC Design Management & HDAP Verification

Article Roundup: Santa’s Autonomous Sleigh, Improving IC Yield Ramp, Silicon Photonics, Custom IC Design Management & HDAP Verification

If Santa had an Autonomous Sleigh Layout schema generation: Improving yield ramp during technology development Realizing the Promise of Silicon…

Article Roundup: PCB Verification in Schematic & Layout, IIoT Architectural Issues, Gender Stereotypes in Tech, Catching HLS Errors Before RTL & the Demise of Reset Buttons

Article Roundup: PCB Verification in Schematic & Layout, IIoT Architectural Issues, Gender Stereotypes in Tech, Catching HLS Errors Before RTL & the Demise of Reset Buttons

Validate Twice, Build Once Architectural Issues for Embedded Devices in the IIoT Overcoming Gender Stereotypes In Tech Catapult Design Checker…