It’s never too late

It’s never too late to fix a design problem.  Well, maybe if the product is shipping, that might be classified as “too late”.  But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues.  When it comes to signal integrity, that means performing pre-layout or post-layout simulations.  I think most experts agree that pre-layout simulations are the best time to do signal integrity.  There those, however, that feel pre-layout simulations are a lot of time wasted on “what might be”, but the counter-argument is that if you don’t simulate, how do you know what constraints to apply to your board layout as it is being layed out.  I say as long as you do EITHER before the product ships, you’ve done well.  But, when it comes to getting products out in the fastest and most efficient manner, a mixture of both pre-layout and post-layout simulation will best suit your needs.

What’s the difference?  Well, other than the obvious fact that post-route simulations are done after layout, I would classify the main difference as the fact that pre-layout simulation is aimed more at exploring a solution space and creating design constraints, while post-layout is aimed at verifying that those constraints were met.  For a more in-depth discussion on the differences, take a look at this article in Electronic Design magazine:
http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/electronic-systems-design/2012/03/29/its-never-too-late/