How STMicroelectronics achieved faster standard cell library verification with AI-powered Solido Library Verifier solution

At the Siemens User2User North America 2026 Conference, STMicroelectronics unveiled impressive results from a new AI-powered methodology developed by the Solido Custom IC team, achieving a 12X speedup in standard cell library verification compared to conventional approaches.

The presentation, authored by Rohit Kumar Gupta, Senior Member of Technical Staff at STMicroelectronics, focused on AI’s role in standard cell verification. Rohit, a seasoned expert with over 18 years of experience in standard cell circuit and layout design, demonstrated how Solido technologies deliver speed and accuracy while remaining practical to deploy.

Challenges with conventional library verification

STMicroelectronics operates across sectors including automotive, industrial, and consumer electronics, supporting a broad range of applications with stringent functional requirements. To optimize power, performance and area (PPA) across their extensive product portfolio, STMicroelectronics designers are increasingly utilizing a broader range of standard cell IP in their designs. However, this expansion combined with the realities of process technology scaling and economic pressures for high yields introduces significant challenges:

• Increased IP diversity: The growing variety of standard cell configurations spanning multiple channel lengths, Vt types, layout styles, and drive strengths, dramatically expands the verification scope and complexity.
• Increased variability: As process technology scales, variability effects such as local mismatch have become more pronounced, leading to an explosion in the number of Process Voltage Temperature (PVT) corners that must be verified to ensure functionality and timing requirements are met.
• High sigma verification (HSV) necessity: Economic pressures to achieve high yields demand HSV, making verification computationally intensive and prohibitively expensive with traditional methodologies.
• Iterative complexity: Standard cell verification is inherently iterative due to design changes, PDK updates, and evolving specifications, compounding the computational burden.
• Manual probing limitations: Conventional approaches required manual probing of internal circuit nodes (e.g., flip-flops) to detect perturbations or glitches. This hindered automation, as designers had to ensure correct internal node names were probed across a broad range of IP with varying topologies and naming conventions.

Addressing library verification challenges with AI

To address these challenges, STMicroelectronics partnered with Siemens EDA with clear objectives:

• Improve runtime significantly
• Maintain or exceed accuracy standards
• Simplify setup and reduce manual intervention
• Report passing yield when achieved yield falls below target

Enter Siemens EDA’s AI-powered Solido Library Verifier solution.

This advanced solution leverages three core technologies:

1. SolidoLibSPICE – A next-generation SPICE simulator designed for accelerated batch verification of library IP designs.
2. SolidoSim AI – Utilizes machine learning and reinforcement learning to provide in-simulator acceleration for yield verification.
3. Solido Additive Learning – Retains and reuses AI models to dramatically speed up iterative workflows.

Together, these technologies deliver meaningful improvements in verification performance, achieving a 12X speedup in standard cell yield verification without compromising accuracy.

Results from Solido Library Verifier

STMicroelectronics tested the solution across three different process technologies:

Performance gains:

• 7X speedup vs. conventional approaches on advanced process node yield verification
• 12X speedup with Solido Additive Learning for iterative runs

Enhanced accuracy:

• Identified five additional failures that were previously undetected, meeting strict accuracy requirements

Seamless automation:

• Eliminated the need for manual probing of internal nodes, enabling full automation and saving significant manual effort

Advanced visualization:

• Device impact reports highlighted sensitive devices and provided insights into critical components with the largest impact on overall sigma values
• Waveform analysis pinpointed exactly where failures occurred, enabling designers to make targeted corrections

Looking to the future

The collaboration between STMicroelectronics and Siemens EDA doesn’t stop here. Both teams are actively working to enhance the solution further through enhancements such as automatic adaptation of batch size to improve the runtime, automatic launch of simulation at the target sigma when the passing sigma falls short, and support for single parameterized netlist for multiple PVT corners.

Watch the full story on demand here.

Learn more about the Solido Custom IC technologies that make up the Solido Library Verifier solution here.