From specification to signoff: Autonomous EDA agents across the design flow

Would you trust an agent with chip design?

The answer depends on more than what the agent can automate or how much time it can save. It depends on whether the agent can operate reliably across the connected workflows semiconductor design requires. These workflows cross tools and engineering domains, involve many interdependent decisions and can run for hours or even days. An agent must maintain context across that entire sequence, evaluate engineering results and determine what should happen next.

That was the central theme of a livestream discussion I hosted with Niranjan “Nero” Sitapure at NVIDIA GTC Berlin. We followed five autonomous workflows, from RTL development and design-for-test to physical implementation, parasitic-aware design closure and advanced 3D IC design.

This article summarizes that discussion and takes a closer look at the workflows and the agentic foundations behind them.

Watch the full GTC Berlin discussion below or read on for the key points.

The foundations of long-running agentic EDA workflows

Before engineers can trust agents with end-to-end workflows, five foundations must be in place: long-running execution; self-verification with human oversight; domain-specific EDA knowledge; secure, sandboxed runtimes; and GPU-accelerated simulation, optimization and verification tools.

The five workflows demonstrated at GTC Berlin put these foundations into practice. They coordinate multiple tools and engineering domains to address recurring challenges identified by engineers, with specialized EDA tools providing the underlying simulation, analysis and verification. The agents maintain context and use engineering results to guide the next step, while engineers retain oversight at critical decision points.

Spec-to-RTL signoff with Questa One Agentic Toolkit and Catapult

The journey begins at the front of the design flow with an autonomous workflow using Questa One Agentic Toolkit and Catapult.

The agent selects the NVIDIA Nemotron 3 Super model and generates a verification plan before creating synthesizable RTL from the specification and synthesizing C++ to RTL. It then executes the verification loop, identifies the root cause of failures using Nemotron and works toward signoff with zero errors.

Generating the initial implementation is only the first part of the task. If verification shows that corner cases have been missed, the agent can return to earlier steps and repeat the necessary work. The workflow connects implementation, verification, coverage analysis, root-cause identification, automated debug and repair and signoff within the same autonomous workflow.

The flow progresses through:

1. Selecting the NVIDIA Nemotron 3 Super model
2. Generating a verification plan
3. Generating synthesizable RTL from the specification
4. Synthesizing C++ to RTL
5. Executing the verification loop
6. Identifying the root cause of failures using Nemotron
7. Verifying signoff with zero errors

At this point, the workflow has produced and verified the RTL. The next step is to make the design testable, which brings the journey to design-for-test with Tessent.

Design-for-test with Tessent

The next workflow uses Tessent to automate DFT RTL insertion and editing, DRC analysis and debug and pattern generation for improved coverage closure.

The agent configures the setup and creates the necessary scripts before running Tessent MemoryBIST insertion. It then creates and inserts test logic, synthesizes the RTL to a gate-level design, adds test points for coverage and pattern size and runs DRC to confirm that the DFT logic is functional.

Running these tasks in sequence requires more than knowing which command comes next. The agent also needs access to the relevant engineering context.

It operates within a defined working environment containing design artifacts such as the specification, RTL and netlist. Skill files provide high-level guidance, while subskill files and MCP tools make more detailed and executable instructions available as they are needed. This gives the agent progressive access to the information it needs without saturating its context window. Throughout the flow, the agent retains the context needed to move from one task to the next.

The flow includes:

1. Configuring the setup and creating scripts
2. Running Tessent MemoryBIST insertion
3. Creating and inserting test logic
4. Synthesizing RTL to a gate-level design
5. Adding test points for coverage and pattern size
6. Verifying that the DFT logic is functional by running DRC

With the RTL verified and the DFT structures in place, the next challenge is physical implementation.

RTL-to-GDS with Aprisa and Calibre

The journey then moves downstream into physical implementation and signoff, connecting Aprisa and Calibre in an autonomous RTL-to-GDS workflow.

The agent runs RTL synthesis, placement and optimization, clock-tree synthesis, post-CTS optimization and routing in Aprisa. The workflow then moves into Calibre for DRC, LVS and parasitic extraction before returning to Aprisa for final timing analysis.

A dashboard tracks the status and results of each stage, providing visibility into the progress of the extended workflow. Additionally, NeMo Gym was used to generate and analyze agent trajectories, helping identify opportunities to refine agent skills and MCP tool descriptions for greater repeatability and token efficiency, and ultimately creating a more optimized workflow.

The agent progresses through:

1. RTL synthesis
2. Placement and optimization
3. CTS and post-CTS optimization
4. Routing
5. Filler insertion and GDS export
6. DRC
7. LVS checks
8. Parasitic extraction
9. Final timing closure

Parasitic effects, including crosstalk, can determine whether the design performs as intended. The next workflow connects parasitic extraction with electrical analysis to support design closure.

Parasitic-aware design closure with Calibre and Solido

This autonomous workflow brings together Calibre and Solido to identify critical nets, extract parasitic effects, analyze electrical behavior and identify worst-case corners.

The flow includes:

1. Using victim and aggressor checks to identify critical nets
2. Performing LVS and floating-gate checks on critical nets
3. Performing layout parasitic extraction
4. Identifying parasitic violations such as crosstalk
5. Running SPICE simulation for transient analysis
6. Identifying worst-case corners through PVTMC simulations
7. Visualizing parasitic violations in the design

In the GTC Berlin discussion, this workflow also raised a broader question: How does the agent verify that the result is functional before moving forward? Across agentic EDA workflows, physics-based engines, workflow-specific verifiers and human review can help confirm that the required engineering process was completed correctly and that the result can be trusted.

The journey to this point has followed the design flow for an individual integrated circuit. In a 3D IC, that challenge expands across multiple ICs, package components, engineering tools, and physical domains.

3D IC electro-thermal design closure and optimization

The final workflow extends the same approach across multiple engineering domains with autonomous electro-thermal 3D IC design closure and optimization.

As AI factories push more compute and memory into increasingly compact systems, advanced 3D IC designs bring interconnected power, thermal, performance and reliability challenges. These considerations cannot be addressed only at the end of the design process. The results of one analysis influence the conditions and decisions applied to the next.

Because 3D IC designs connect multiple ICs horizontally and vertically, they introduce interconnected thermal, mechanical, electrical and interconnect considerations. This workflow focuses on connecting power, thermal, parasitic and electrical analyses as part of a multi-domain, multiphysics process.

In this workflow, Claude Code is the coding agent and orchestrates a nine-stage electro-thermal flow across seven Siemens EDA tools, with the tools exposed through an aggregate MCP server provided by Fuse EDA AI Agent.

The flow develops the 3D IC design and package components, generates new Liberty files, and performs power analysis. It then creates a power map, uses design-space exploration to identify thermal hotspots and optimal temperature, performs parasitic extraction and runs power- and temperature-aware SPICE simulation.

At a high level, this agentic 3D IC workflow brings together:

1. Development of the 3D IC design and package components
2. Characterization and generation of new Liberty files
3. Power analysis
4. Power-map generation using a grid search
5. Identification of thermal hotspots and optimal temperature using design-space exploration
6. Parasitic extraction
7. Power- and temperature-aware SPICE simulation

The workflow demonstrated:

• Up to 95% reduction in engineering effort
• 20 times faster workflow configuration
• Up to 50 times more design-space exploration coverage

The flow brings together Innovator3D IC Integrator, Solido Characterizer, mPower Digital, Calibre 3DThermal, Simcenter FloTHERM, Calibre xACT and Solido SPICE.

This demo shows agentic orchestration across a broader engineering scope. Rather than connecting consecutive stages for an individual IC design, the workflow brings together analyses from multiple engineering domains, with the output of one stage informing what happens next.

How Siemens and NVIDIA are making long-running EDA agents reliable and token-efficient

Long-running execution creates its own engineering challenges. Agents must retain context across many interactions, continue operating reliably when individual steps do not proceed as expected, validate their decisions and operate efficiently within secure environments.

Siemens and NVIDIA are addressing these requirements through a combination of NVIDIA AI technologies and accelerated computing. NeMo Gym helps teams analyze agent trajectories and refine agent skills and MCP tool descriptions. Nemotron open models and NeMo RL support cost-efficient execution and post-training with domain-specific EDA knowledge, while NeMo Relay provides observability and auditability across agent runs. NVIDIA OpenShell securely sandboxes agent execution, and CUDA-X libraries accelerate supported physics-based engineering solvers used for simulation and verification.

Read the Siemens and NVIDIA technical blog on optimizing long-running engineering agents.

Watch the GTC Berlin discussion with Siemens and NVIDIA for a deeper look at the technologies behind reliable and token-efficient engineering agents.

Where the engineer-agent relationship goes next

The journey began with a written specification. From there, the workflows generated and verified RTL, inserted test structures, implemented the physical design, evaluated parasitic effects and extended the same approach across the connected electrical and thermal challenges of 3D IC design.

Throughout the journey, specialized EDA tools provided the underlying simulation, analysis and verification, while the agents connected the tools, maintained context and used the results to guide each workflow.

As the discussion drew to a close, Nero considered what increasingly broad, long-running workflows could mean for engineering teams:

“The future is not one engineer to one agent. It is one engineer to many agents.”
Niranjan “Nero” Sitapure, Central AI Product Manager, Siemens EDA

Engineers could initiate multiple agents to explore alternatives in parallel while spending less time on repetitive setup and debugging. Reusable tools, skills and subflows could become building blocks that teams combine around different engineering objectives.

This does not remove engineers from the process. It changes where their expertise is applied. Engineers remain responsible for architectural decisions, engineering tradeoffs, oversight and approvals, while agents execute repetitive workflow steps and bring the relevant engineering results forward for review.

Together, these demos show the breadth of what long-running, self-verifying agents can take on across some of the most common and complex parts of the semiconductor design flow. Their value lies not simply in the amount of work they can execute, but in their ability to coordinate that work while remaining grounded in physics-based EDA tools, verifiable engineering results and human oversight.