From complexity to clarity: Simplifying AMS verification with Mixed-Signal Visualizer
A fundamental principle from operations theory teaches us that optimizing the bottleneck or critical path of any process yields the most significant benefits. This principle strongly applies to the process of integrated circuit (IC) design. With chip design and verification, the debug process has emerged as a major bottleneck, with a study estimating it consumes around 47% of the overall verification time for a typical application-specific integrated circuit (ASIC) design. For analog mixed-signal (AMS) designs, this challenge is further compounded, as engineers must correlate continuous analog behavior with discrete digital logic across complex architectures and multiple abstraction levels.
Traditional debug tools which often rely on waveform analysis and test reports and log files are simply not equipped to handle this escalating complexity. They offer limited visibility and inefficient workflows, leaving engineers searching for a more robust solution. At Siemens EDA, we identified the critical need for an intuitive environment capable of handling diverse modeling formats and intricate boundary element configurations, and to support industry-standard methodologies like Unified Power Format (UPF) and Universal Verification Methodology (UVM).
A new approach to AMS debugging
Symphony Pro, part of Solido Simulation Suite, features the Mixed-Signal Visualizer (MS Visualizer), a graphical debug environment that is purpose-built to address the challenges of modern AMS verification. It features a rich set of capabilities including:
Multi-window design visualization: Enables IC verification engineers to obtain a holistic view of design, with dedicated windows for hierarchy, netlists, source code, and variables, all dynamically updated as the user navigates. This clarity is particularly valuable for navigating through complex “sandwich” structures where analog and digital blocks are interleaved within the design hierarchy which is a common feature of modern IC designs.
Automatic schematic generation: MS Visualizer can automatically generate schematics, making it easy to visualize connectivity, verify port mappings, and quickly identify inconsistencies in large, hierarchical designs.
Mixed-signal net analysis: For signals crossing analog and digital domains, MS Visualizer provides both analog and digital representations, allowing verification engineers to confirm proper conversion behavior (A2D or D2A) and pinpoint issues with boundary elements.
Issue resolution: MS Visualizer accelerates issue resolution by providing deep observability and an intuitive debug workflow, helping teams reduce verification time, stay on schedule, and deliver designs to market faster.
Ready to dive deeper?
For a detailed look at how MS Visualizer can streamline your AMS verification, read the full whitepaper. It includes case studies that demonstrate the effectiveness of MS Visualizer on real customer designs.
Learn more about Solido Simulation Suite here
