Multi-die verification: the chiplet simulation challenge

The shift towards chiplet-based architectures has fundamentally changed how we verify integrated circuits. When multiple dies, potentially from different vendors and different process nodes, come together in a single package, traditional simulation approaches fall short.

The simulation challenge breaks down into three main areas:

1. Different process nodes
   Multi-die systems often combine chiplets built on different process nodes. A chip designer might pair a 3nm node compute die with a 7nm I/O die and HBM chiplet in 1α (1-alpha) nm node, for instance. This creates an immediate verification problem: you need SPICE-accurate simulation across different PDKs simultaneously. The integrator must verify cross-sections between these disparate technologies and not just rely on interface IP specifications or connectivity checks, ensuring they work together despite being designed with different foundry tools and models.
   
   
2. Signal integrity across boundaries
   Transceivers serve as the critical gateway between chiplets and external memory. But verifying these links requires accounting for the complete signal path: through the die itself, through interposers, across package substrates, and onto the board. Each interface introduces its own challenges such as crosstalk, distortion, power, noise, jitter, etc. For final signal integrity signoff, you need to verify the entire channel, including receiver equalization to ensure an open eye that is compliant with specifications. 
   
   
3. Mixed-signal complexity
   Multi-protocol I/Os and SerDes PHYs blend analog and digital circuitry across multiple power domains. These aren’t purely digital blocks you can verify with standard logic simulation, nor purely analog circuits amenable to simple SPICE runs. They require mixed-signal verification that can handle both domains simultaneously and across the complete die surface. These communication PHYs directly impact overall chip power, performance, and area (PPA), so getting them right is critical for tape-out. 

The verification engineer’s reality

With all of this in mind, verifying a complete die-to-die I/O channel from end to end presents a massive challenge with both feasibility and accuracy within integration schedules. Transceivers are critical gateways at die boundaries, whether designed with a source-synchronous clock forwarding or a clock recovery scheme for high-speed data transmission and reception. This applies to any communication protocol such as DDR, HBM, PCIe, CCIX, CXL, SATA, USB, etc., for which PHY-based IP are required. 

Further, PHY designs are built with analog components interlaced with digital logic, and multi-voltage domains. Increasing parasitics and variability with advancing process nodes dictates the need for variation-aware and high-capacity simulation technologies. This in fact applies to all analog components on the die such as PLLs, clock tree paths, voltage regulators etc., that need to adhere to stringent specifications. 

Verification engineers need to design to SPICE-level accuracy that accounts for intended signal effects, as well as unintended ones like crosstalk and coupling, power supply fluctuations and noise and temperature variations. Jitter budgets need to be met for clocking IP, where random and deterministic jitter of components within need to be accurately quantified. All of this needs to be done in a timely fashion to enable design iterations for circuit robustness and final IP signoffs to achieve first-time-right (FTR) tapeouts in a competitive semiconductor market.   

The Solido approach to multi-die verification 

Meeting all these requirements simultaneously is where many existing verification flows struggle, and where the choice of simulation toolset becomes critical. Solido Simulation Suite addresses these challenges through integrated capabilities designed with multi-die verification in mind: 

• Multi-technology simulation: Solido Simulation Suite and Solido Design Environment together handle verification of circuits with different process nodes in a single unified flow, allowing designers to view waveforms across multiple process cross-sections.  

• Die-to-die link verification: Solido SPICE provides SPICE-accurate simulation of inter- and intra-die links from transmitter through receiver front-end, including channel and equalization effects, ensuring that what works in isolation will work in the integrated system. 

• Comprehensive analysis: Solido SPICE provides transient, noise, RF periodic-steady state (PSS) and harmonic balance (HB), and aging analyses, allowing designers to verify functionality, power consumption, and jitter. 

• S-parameter integration: Solido SPICE offers advanced handling of S-parameters, enabling accurate modeling of die, interposer, package and board routes, the physical key paths that connect your chiplets, memory and external systems. 

• Unified mixed-signal verification: Symphony analyzes analog and digital together, with debugging and visualization tools and a configurable architecture for analog and digital simulators, reducing the iteration cycles typically needed to track down cross-domain issues. 

Multi-die verification checklist 

As you plan your next multi-die project, consider if your verification tools: 

1. Can simulate different process nodes together (multi-technology/PDK support) 
2. Verify the complete IO channel, not just isolated pieces (full-path accuracy)
3. Handle analog PHYs and digital logic in one flow (mixed-signal capability) 
4. Cover transient behavior, noise, jitter, and aging in one environment (analysis breadth) 

If any of these are gaps in your current flow, it’s worth exploring simulators that address them.