See you at TSMC 2017!

See you at TSMC 2017!

It’s that time of year again…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

What to see at SPIE 2017

What to see at SPIE 2017

It is time again for the SPIE Advanced Lithography conference.

DFM Line-End Enhancement with Calibre Pattern Matching

DFM Line-End Enhancement with Calibre Pattern Matching

Using Calibre Pattern Matching to add line-end extensions to a design is a simple way to improve yield and reliability,…

How to choose LVS box flow

How to choose LVS box flow

How do you decide which kind of LVS BOX flow makes sense for what you want to accomplish? Watch this…

Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

Creating an initial Hcell list for Calibre LVS jobs, using Calibre Interactive

Creating an initial Hcell list for Calibre LVS jobs, using Calibre Interactive

Need an hcell list for your hierarchical design? You can use the Calibre Interactive tool to quickly and automatically create…

Using Automated Pattern Matching For SRAM Physical Verification

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.