Do my database merges make my runtimes too slow?

By Saunder Peng – Mentor, A Siemens Business

Merging databases often creates bottlenecks in the design and verification flow, wasting time and resources and destroying schedules. Widely adopted in IC design houses and foundries, the Calibre DESIGNrev layout filemerge functionality is a proven solution that significantly reduces runtime while providing accurate results.

Running physical verification is critical in each stage of a design flow, and it requires a complete design database to ensure a valid run. What, exactly, does that mean? A complete design database should contain the most up-to-date intellectual property (IP) design data merged with the top-level reference design data, and a fill database merged with the design database.

But, merging today’s huge databases can take hours, or even days. Is there a better way?

In a typical design process, there are three stages when it is necessary to merge databases:

  • replacing P&R top-level abstracts with GDS IP/blocks
  • merging fill with the top-level design
  • updating IP/blocks to the most recent versions

Merging a P&R database with design IP/block data is typically done with layout design tools or with P&R tools. The biggest problem with this approach? Neither of these tools is optimized for database merging. The results are usually long runtimes and high memory consumption.

Fill databases are usually created with DFM tools, then merged with the design data using design tools. Typically, this means converting both databases to an OpenAccess format before merging, adding the conversion time to tight delivery schedules.

When a block/IP is updated, it must be merged into the full-chip database, or all physical verification and fill results will be invalid. These full-chip database updates typically happen weekly, but sometimes even daily. Whether you choose to merge both databases from the beginning of the design cycle, or swap in the updated IP/block data to a previously-merged database, you are looking at a long execution time.

But what if there was a tool that could solve these merge problems automatically? The Calibre DESIGNrev layout filemerge functionality handles format conversions and database merging quickly and efficiently to minimize runtimes:

  • The ability to directly merge databases in both GDSII and OASIS format eliminates the need to convert databases to a different format prior to merging
  • Low memory consumption allows users to merge databases with minimum machine requirements
  • Using a single command to combine thousands of IPs with top-level P&R databases enables fast, accurate full-chip database updates

If you’re running multiple merges during each design iteration, incorporating Calibre DESIGNrev layout filemerge into your database merge flow can potentially reduce the design cycle by days, achieving a quick turnaround time with an optimized design. Want to see how it’s done, and learn about some of the other benefits of using the Calibre DESIGNrev layout filemerge approach? It’s explained in detail in our white paper, Database Management for Design Verification Flows.


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This article first appeared on the Siemens Digital Industries Software blog at