Improve interconnect robustness with Design Enhancer’s automated via insertion

By Shehab Ashraf

At advanced nodes, issues like via resistance, electromigration (EM), and IR drop can leave little margin for meeting performance and reliability targets. When they surface late, fixes often mean another round of design work, and added pressure on the schedule.

What if teams could identify and address these issues earlier in the design cycle?

The power of shift-left with Calibre DE-Via

The “shift-left” strategy is transforming how engineers approach physical design. By moving signoff-aware optimizations into the implementation phase, teams can identify and resolve potential issues before they become costly bottlenecks.

A key component of this strategy is Calibre DesignEnhancer Via (DE-Via). This automated tool is designed to improve interconnect robustness and power delivery by automating the insertion of redundant vias. By integrating this process directly into the implementation flow, designers can ensure that their layouts are optimized for reliability long before they reach final verification. Figure 1 illustrates the flow.

Flowchart illustrating the DE-Via process: from extracting valid fill regions based on metal intersections to performing DRC-clean via insertion within those regions — Figure 1. DE-Via automated via insertion flow. From extracting and detecting the valid fill regions based on the metal intersections on the target net to performing the DRC-clean via insertion within that region.

Why automated via insertion matters

Implementing an automated approach to via optimization provides several critical advantages that directly impact both design quality and project timelines.

Interconnect robustness: DE-Via addresses via resistance and EM challenges by strategically adding redundant vias, ensuring a more reliable connection throughout the design.

Improved power delivery: By optimizing via placement, the tool helps mitigate IR drop, ensuring that power is delivered efficiently to all parts of the chip.

Foundry-clean results: Unlike manual or generic automated methods, DE-Via is signoff-aware. This means every modification is DRC-clean and fully compliant with foundry rules, eliminating the risk of late-stage surprises.

Schedule compression: By automating a traditionally manual and time-consuming process, DE-Via significantly reduces design cycle time allowing teams to meet aggressive deadlines without compromising on quality.

Expanding the capabilities of Calibre DesignEnhancer

Calibre DesignEnhancer is more than just a via-insertion tool; it is a comprehensive platform for layout optimization. By utilizing the industry-standard Calibre engine, it provides a level of precision that implementation tools often lack.

Signoff-quality engines: Calibre DE uses the same engines as Calibre nmDRC and Calibre nmLVS. This ensures that any layout modification made by the tool is “correct-by-construction” and will not trigger violations during the final signoff run.
Flexible integration: The tool supports standard design formats such as LEF/DEF, GDS and OASIS. This allows it to fit seamlessly into existing P&R flows, enabling designers to run enhancements iteratively as the layout matures.
Targeted enhancement: Designers can choose to run DE-Via on specific high-priority nets, such as clock trees or critical signal paths, or apply it across the entire design to maximize overall reliability.

Overcoming layout imperfections with short-resilience

One of the most significant challenges in a shift-left flow is that the layout is often “dirty” or incomplete when enhancements are most needed. Traditional tools often fail or produce unpredictable results when faced with localized connectivity conflicts, such as routing overlaps or shorts.

Calibre DE-Via addresses this with its short-resilient capability. This feature allows the tool to proceed with via optimization even when the design data contains localized shorts. The flow automatically identifies these short-prone regions and converts them into “insertion keep-out areas.” Figure 2 presents two different types of shorts. The top figure is a short through vias: Different net shapes overlapping on neighboring layers with any VIA between them. The bottom is indirect shorts between one of the specified nets and any other nets (routing/special) through a LEFPIN.

Visual examples of different short types, including direct shorts through vias in GDS/OASIS formats and indirect shorts through LEFPINs in LEF/DEF designs — *Figure 2. Different types of shorts: shorts through vias, typically found in GDS/OASIS layout formats and indirect shorts through LEFPINs, typically found in LEF/DEF designs.*

By protecting these suspicious locations, the tool can continue to insert redundant vias in all other valid areas of the design. This short-resilience ensures that productivity isn’t stalled by minor layout issues, allowing design teams to continue improving robustness without requiring a perfectly clean database at every step.

Addressing the advanced-node bottleneck

As designs transition to 5 nm and below, the complexity of foundry rules grows exponentially. Manual via insertion is no longer just tedious; it is practically impossible to execute at scale while remaining DRC-clean. Generic router-based solutions often lack the signoff awareness needed to handle these complex constraints, leading to a “whack-a-mole” scenario where fixing one issue creates three new violations.

Calibre DE-Via solves this by leveraging the industry-standard Calibre engine during the enhancement process. It evaluates the local layout environment in real-time, ensuring that every redundant via added is legally placed. This level of precision allows designers to maximize via density, and therefore robustness, without the fear of introducing late-stage ECOs.

Maximizing reliability through automation

The benefits of automated via insertion extend beyond just meeting DRC rules. By increasing the number of parallel paths for current, DE-Via significantly lowers the overall resistance of the interconnect. This not only improves the EM profile of the design but also provides a safety margin against manufacturing variations. In a competitive market, this extra layer of reliability can be the difference between a successful product launch and a costly redesign.

Furthermore, the tool’s ability to process standard design formats like LEF/DEF and OASIS makes it easy to integrate into existing EDA environments. Whether you are working on a small block or a full-chip SoC, the scalability of DE-Via ensures that your interconnect robustness scales with your design.

Building a signoff-ready design

The goal of any physical design team is to reach a signoff-ready state as quickly and efficiently as possible. By integrating Calibre DE-Via into your workflow, you’re not just adding vias – you’re building a foundation for a more robust, reliable and high-performing product. Shifting signoff left isn’t just a methodology; it’s a competitive advantage that ensures your design is ready for the challenges of advanced-node manufacturing.

Ready to learn more about how Calibre DE-Via can transform your design process? Check out our latest white paper: Shifting signoff left for robust physical design with automated via insertion.