Today’s ERC demands new verification capabilities to ensure product reliability and performance

By Derong Yan – Mentor, A Siemens Business

Today’s advanced ERC requires an EDA tool that can automatically understand complex connectivity and in-context device information. Just like the Calibre PERC reliability platform…   

Traditional ERC verifies simple electrical design rules, such as floating wells and bad device construction, using basic connectivity and device information. However, in today’s IC designs, we often need to check more complex ERC issues, including latch-up, noise immunity, floating pins, cross-power-domain verification, and leakage current, among others. When such issues are combined with advanced manufacturing processes, SoCs, and multiple power domains, ERC becomes much more challenging, primarily because of the in-context information required by many of these ERC checks. Simulation tools such as SPICE are only helpful to a limited extent, because they require precise setup to expose subtle design issues, and lack the scalability needed for today’s large SoC designs, which often contain billions of transistors.

Without a full set of advanced ERC checks, companies risk releasing products that do not perform as designed, or experience premature failure in the field. Advanced automated circuit verification for electrostatic discharge, electrical overstress, multiple power domains, advanced ERC, and many other reliability concerns not only needs to understand the more complex connectivity and greater design context required by advanced ERC rules, but also must deliver the scalability needed for large SoC designs. By enabling sign-off quality, automated context-aware verification for today’s most challenging electrical design rules, the Calibre PERC reliability platform empowers design companies to deliver reliable, robust products on schedule and on budget, while providing the performance and product life the market demands.

For more details, view or download a copy of our white paper, Advanced electrical rule checking in IC reliability verification

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