By Tarek Ramadan – Mentor, A Siemens Business
As the use of HDAP grows, so does the need for post-layout electrical analysis. Automated flows that generate an HDAP netlist for simulation and STA analysis could be useful, don’t you think?
As HDAP technologies become more and more similar to IC technologies, it is clear that, although the physical verification steps for HDAP may be considered good progress, they are only part of a much more comprehensive flow, one that must account for a more in-depth, system-level electrical analysis. Foundries and OSATs now expect that each component in an HDAP has been designed and validated to meet all the required HDAP constraints and specifications. What does that mean?
For example, in a digital-based flow, the designer must run static timing analysis (STA) on the complete HDAP system, including parasitics, to ensure it meets the overall system timing budget. That requires generating a system-level netlist, accruing the die-level and package-level layout parasitics, extracting the coupling capacitance between each die and the package, generating an annotated interface database and the interface RC models, then finally creating a layout netlist annotated with the interface parasitics.
Is that all? Whew! The good news is that EDA suppliers now have tools and functionality that can perform all of these tasks for you. In fact, Mentor provides a complete, proven flow that generates HDAP system-level connectivity while accounting for die, package, and die/package interface parasitics.
If you’d like to learn more about system-level electrical analysis for HDAP designs, download a copy of our white paper, System-level, post-layout electrical analysis for high-density advanced packaging. It explains each requirement in detail, to help you better understand how to build HDAPs with the confidence that they are compliant with the foundry/OSAT requirements and recommendations.