Automate those voltage-dependent DRC checks!

By Design With Calibre

By Beth Martin with Dina Medhat, Mentor Graphics

 What do all these new voltage-dependent DRC rules mean, and how do I implement these checks?

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Because IC design and verification never gets simpler, verification engineers now have to comply with voltage-dependent DRC (VD-DRC) rules. What does this term mean, and what new challenges does it bring to the DRC task? I’d like to share what I learned during another water-cooler conversation with Dina Medhat, senior technical marketing engineer at Mentor.


DM_Automate_Fig1VD-DRC rules require different spacings based on either the operating voltage on the geometries being checked, or the difference in voltages between different geometries (wires) running next to each other. Because there might be many voltage domains and voltage differentials in a modern SoC design, a designer can no longer apply just one spacing rule per metal layer.


The traditional challenge, says Medhat, is how to get the voltage information for each net to apply the appropriate spacing rule. She said customers often ask questions like, “How can we create an automated solution to this checking task?” Or more specifically, “How can we capture the voltage information without having designers add layout markers to designate them?” Before answering these questions, let’s have a deeper look at the technical problem that they’re facing.


In VD-DRC, spacing requirements between nets are determined by the operating voltages present on the nets. But, how do you define these voltages in a layout? The best-known method is to add markers (either text layers or polygons) to the layout with the expected voltage value. Because the designer must add the correct marker manually, the process is subject to human error. If the markers are not present, or they are incorrectly placed, false violations can occur. These false errors can be very difficult and time-consuming to debug, which is a waste of time and resources. But even worse, marker errors can result in rule violations that sneak by the check, and result in device failure down the road. Moving to more complex designs and advanced process nodes, says Medhat, greatly increases the complexity of VD-DRC and the challenge of defining voltages in a layout.


Checking errors that are introduced during DRC because of improper rule coding or erroneous voltage markers can generate hundreds of errors that need to be analyzed and debugged, and the false DRC violations then need to be waived by the designer, which introduces even more time and overhead. Inaccurately marked layouts can also result in substandard routing optimizations, if the router uses general worst case rules, rather than rules based on the actual voltages present on various nets of the layout.


Medhat wants to solve VD-DRC challenges with an automated flow that can propagate realistic voltage values to all points in the layout, eliminating the more fallible manual process. Mentor has worked directly with customers to build such a flow based on Calibre PERC. “The VD-DRC flow first identifies the supply voltages for the design, and then uses a voltage propagation algorithm to determine the voltages on internal layout nodes,” says Medhat. “The voltages are computed automatically based on static propagation rules, which can be user-defined for specific device types. The algorithm is applied to the netlist to identify target nets and devices needed for VD-DRC.”


DM_Automate_Fig2Because the netlist information is preserved along the entire flow, the results are context-specific, making them easy to debug. This integration between netlist, connectivity-based voltage analysis, and geometric analysis is important. Once the node voltages are computed, the tool writes out the voltage information as text markers into a separate file, which is given as an input to the Calibre tool running the DRC sign-off deck.


This automated flow doesn’t require any changes to sign-off decks, and it generates the voltage information automatically, without requiring any manually added physical layout markers. This approach reduces both the design team workload, and the chance of missing real violations or producing false violations.



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