This course will try to cover the entire System Verilog language with examples that learners can connect the concepts with. It focuses on the key features of language and how to use them. Features include:
- Significant additions from Verilog
- What are they used for and how they are used
- Features that are useful for design and verification
- Lab exercises using Questa/ ModelSim
Note this is not a course on design or verification. A strong background in Digital Design and SystemVerilog HDL programming is recommended.
Check another one of our free classroom resources on emerging functional verification methods here.
Siemens Global Academic Partner Program empowers the next generation of digital talent with
Curriculum Hub for Free Classroom Resources
Academic Certifications and Digital Badges – Get certified in NX, Solid Edge, Simcenter Amesim, MBSE and more
Software Downloads – Free software for students and educators!