Joe Hupcey III

I am a product marketing and management professional, who brings a unique combination of hands-on engineering experience, an insightful understanding of what customers need in today’s ever-growing complex environment, and a proven ability to create winning messages that differentiate my company’s offerings from those of the competitors’. The context of this activity is the high-stakes race for more powerful chips and systems, whose complexity continues to double every 18 months even today.

From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025

From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025

September 17, 2025
In support of Verification Academy’s educational mission, Siemens is either directly sponsoring or contributing to the following five tutorials at...
By Joe Hupcey III
< 1 MIN READ
Class is back in session this October: Verification Academy’s cutting-edge weekly webinar series

Class is back in session this October: Verification Academy’s cutting-edge weekly webinar series

September 16, 2025
Verification Academy’s fall semester starts this October with the following series of weekly deep dive webinars. Abstracts and registration links...
By Joe Hupcey III
< 1 MIN READ
GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)

GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)

March 10, 2025
Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new...
By Joe Hupcey III
< 1 MIN READ
GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

March 5, 2025
Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require...
By Joe Hupcey III
< 1 MIN READ
The osmosis formal verification conference celebrates its 5th anniversary this October 17!

The osmosis formal verification conference celebrates its 5th anniversary this October 17!

September 26, 2024
Calling all formal verification enthusiasts: We are excited to invite you to osmosis 2024, marking the 5th anniversary of this...
By Joe Hupcey III
< 1 MIN READ
Learn About the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

Learn About the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

June 4, 2024
The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle...
By Joe Hupcey III
< 1 MIN READ
osmosis – our annual event for formal verification users – is coming-up on November 16!

osmosis – our annual event for formal verification users – is coming-up on November 16!

October 26, 2023
Attention anyone interested in Formal Verification: We are thrilled to invite all formal verification enthusiasts to osmosis 2023, the premier...
By Joe Hupcey III
< 1 MIN READ
<strong>3 Ways DVCon US 2023 is Going to be Different This Year</strong>

<strong>3 Ways DVCon US 2023 is Going to be Different This Year</strong>

February 21, 2023
1 – The Tuesday keynote For the first F2F/IRL DVCon since 2020, the Steering Committee wanted a fresh alternative to...
By Joe Hupcey III
< 1 MIN READ
Osmosis – our annual event for formal verification users – is back F2F this December 8, 2022!

Osmosis – our annual event for formal verification users – is back F2F this December 8, 2022!

October 18, 2022
Attention anyone interested in Formal Verification: after a hiatus due to you-know-what, osmosis is back in-person this coming December 8...
By Joe Hupcey III
< 1 MIN READ
How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

How to Mitigate the Impact of Security and Safety Flaws on Automotive ICs

June 30, 2022
Nearly 7 years ago security researchers uncovered how to remotely access and control the steering, cruise control, and braking system...
By Joe Hupcey III
< 1 MIN READ
DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All?

DAC 2022: The Digital Twin Reimagined – One Model To Rule Them All?

June 21, 2022
To many of us in the EDA world, using the term “digital twin” to describe how customers’ electronically model their...
By Joe Hupcey III
< 1 MIN READ
DAC 2022: Siemens EDA Experts Share Practical Cloud Solutions

DAC 2022: Siemens EDA Experts Share Practical Cloud Solutions

June 15, 2022
Customers have been running Siemens EDA’s tools and flows in the cloud since 2005; and today at any given time...
By Joe Hupcey III
< 1 MIN READ
Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference

Learn How to Verify PCIe Integrity and Data Encryption (IDE) Security Logic at the 2022 PCI SIG Developer Conference

June 9, 2022
Making sure that digital logic enables secure data to safely flow through a system is a critical task for RTL...
By Joe Hupcey III
< 1 MIN READ
Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

Pro Tip: Planning to Land Your Spacecraft on Mars? You Will Need CDC, RDC, and Formal Property Checking

May 19, 2022
If you are an engineer at one of the growing number of entities looking to land a spacecraft on Mars...
By Joe Hupcey III
< 1 MIN READ
Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

Do You Know for Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

March 28, 2022
Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading...
By Joe Hupcey III
< 1 MIN READ
Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Preview of DVCon 2022 — How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

February 21, 2022
With eight papers in two separate sessions focused exclusively on formal verification, one could assert (pun intended) that this year’s...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

The Many Flavors of Equivalence Checking: Part 6, FPGA-focused Equivalency Checking Flows

February 2, 2022
With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many...
By Joe Hupcey III
< 1 MIN READ
Build Your Career by Attending the Static & Formal Verification University at DAC 2021

Build Your Career by Attending the Static & Formal Verification University at DAC 2021

December 1, 2021
Among the reasons to go to university are the opportunities to open new career paths by learning new technical skills,...
By Joe Hupcey III
< 1 MIN READ
How Can You Say That Formal Verification Is Exhaustive?

How Can You Say That Formal Verification Is Exhaustive?

September 16, 2021
As a companion to my previous post on Learn Formal the Easy Way, allow me to explain what are often...
By Joe Hupcey III
< 1 MIN READ
Learn Formal the Easy Way

Learn Formal the Easy Way

August 31, 2021
The sight of kids going back to school can prompt feelings of joy and renewal – or trigger less pleasant...
By Joe Hupcey III
< 1 MIN READ
DVCon U.S. 2021 Best Paper Report – Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

DVCon U.S. 2021 Best Paper Report – Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

March 31, 2021
This year’s DVCon U.S. saw many great papers, posters, and tutorials; covering almost every aspect of functional verification. Thus, in...
By Joe Hupcey III
< 1 MIN READ
3 Notable Formal Verification Conference Papers of 2020

3 Notable Formal Verification Conference Papers of 2020

February 9, 2021
On the short list of positive things to come out of the past year are the formal verification-focused conference papers...
By Joe Hupcey III
< 1 MIN READ
Reducing Area and Power Consumption while Increasing Performance with Formal-based ‘X’ Verification

Reducing Area and Power Consumption while Increasing Performance with Formal-based ‘X’ Verification

October 7, 2020
[Preface: on October 15 at 8am Pacific, Product Engineer Ping Yeung will be delivering a free, detailed technical webinar on...
By Joe Hupcey III
< 1 MIN READ
DAC 2020 Paper Report: Easy Deadlock Verification and Debug with Advanced Formal Verification

DAC 2020 Paper Report: Easy Deadlock Verification and Debug with Advanced Formal Verification

August 4, 2020
At this year’s Design Automation Conference (DAC), Formal verification was everywhere – in posters, papers, and panel discussions – where...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 5, Summary of the Most Popular LEC and SLEC Use Cases

The Many Flavors of Equivalence Checking: Part 5, Summary of the Most Popular LEC and SLEC Use Cases

July 13, 2020
As I noted at the beginning of this series, the term “logic equivalence checking” (LEC) applies to a number of...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification

The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification

May 19, 2020
[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, Part 2 describes how...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

March 23, 2020
[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes...
By Joe Hupcey III
< 1 MIN READ
FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

December 3, 2019
[Preface: I briefly interrupt my series on The Many Flavors of Equivalence Checking to share this report on an important...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

August 20, 2019
Perhaps the only Sequential Logic Equivalence Checking (SLEC) flow that is as common as the synthesis validation flow described in...
By Joe Hupcey III
< 1 MIN READ
The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

July 11, 2019
In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 6 – Leveraging Data Independence and Non-Determinism

How to Reduce the Complexity of Formal Analysis – Part 6 – Leveraging Data Independence and Non-Determinism

November 1, 2018
If you know the dependencies – or lack thereof – in your design, you can exploit two very fundamental characteristics...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

How to Reduce the Complexity of Formal Analysis – Part 5 – Memory Abstraction

October 23, 2018
When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

How to Reduce the Complexity of Formal Analysis – Part 4 – Counter Abstraction

September 28, 2018
When big counters and memories are in the active logic cone of an assertion that keeps coming up as “inconclusive”,...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 3 – Assertion Decomposition

How to Reduce the Complexity of Formal Analysis – Part 3 – Assertion Decomposition

September 11, 2018
In Part 2 of this series, we showed how reducing the complexity of you assumptions (a/k/a constraints) can really help...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

How to Reduce the Complexity of Formal Analysis – Part 2 – Reducing the Complexity of Your Assumptions

August 22, 2018
When using formal property checking, users often encounter “inconclusive” results; meaning the combined complexity of the design, assertions, and assumptions...
By Joe Hupcey III
< 1 MIN READ
How to Reduce the Complexity of Formal Analysis – Part 1 – Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take

How to Reduce the Complexity of Formal Analysis – Part 1 – Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take

August 8, 2018
When using formal property checking, users often encounter “inconclusive” results; which means that the combined complexity of the design, assertions,...
By Joe Hupcey III
< 1 MIN READ
Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

Significantly Improve Your FPGA Design Reliability by Using Custom CDC Synchronizers

April 24, 2018
[Preface: we are presenting a paper on this topic at the upcoming SEE/MAPLD conference, May 21-24, 2018 in La Jolla,...
By Joe Hupcey III
< 1 MIN READ
OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

OVL: The Free, Open Assertion Library You Can Use To Jump Start Your Formal Testbench

March 26, 2018
You’ve watched all the Verification Academy videos on getting started with formal verification, and even tried some of the examples...
By Joe Hupcey III
< 1 MIN READ
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

February 13, 2018
[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the issues raised below, as well...
By Joe Hupcey III
< 1 MIN READ
Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

Formal Tech Tip: What are Vacuous Proofs, Why They Are Bad, and How to Fix Them

December 6, 2017
In formal verification, proving all of your properties is pretty much the main goal of the whole exercise – if...
By Joe Hupcey III
< 1 MIN READ
How to Save a Ton of Time and Energy by Prioritizing Faults with Exhaustive Formal Analysis Before Launching Detailed Fault Verification

How to Save a Ton of Time and Energy by Prioritizing Faults with Exhaustive Formal Analysis Before Launching Detailed Fault Verification

October 23, 2017
[Preface: If you are going to be at ARM Techcon 2017 on Wednesday October 25, the methodology described in this...
By Joe Hupcey III
< 1 MIN READ
DVCon China: Formal Technology Is Set for Growth in Asia

DVCon China: Formal Technology Is Set for Growth in Asia

May 8, 2017
At the recent DVCon in Shanghai, China, my colleague Jin Hou delivered the tutorial “Back to Basics: Doing Formal the...
By Joe Hupcey III
< 1 MIN READ
How To Connect Your Testbench to Your Low Power UPF Models

How To Connect Your Testbench to Your Low Power UPF Models

January 5, 2017
Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL....
By Joe Hupcey III
< 1 MIN READ
How Formal Techniques Can Keep Hackers from Leaving You in the Cold

How Formal Techniques Can Keep Hackers from Leaving You in the Cold

November 15, 2016
While internet connected vehicles remain a popular target for hackers, the new breed of “smart” devices have the potential to...
By Joe Hupcey III
< 1 MIN READ
3 Things About UPF 3.0 You Need to Know Now

3 Things About UPF 3.0 You Need to Know Now

September 6, 2016
UPF 3.0 has been an official IEEE standard since January, but its most valuable capabilities have only become clear as...
By Joe Hupcey III
< 1 MIN READ
How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC

How to Avoid Metastability on Reset Signal Networks, a/k/a Reset Check is the New CDC

July 21, 2016
It’s axiomatic that digital circuitry must initialize properly before it’s used. Once upon a time, verifying a design’s reset signaling...
By Joe Hupcey III
< 1 MIN READ
5 Things I Learned at the 2016 SAE World Congress

5 Things I Learned at the 2016 SAE World Congress

May 10, 2016
A few weeks ago I had the honor of presenting a paper related to my prior Verification Horizons blog posts...
By Joe Hupcey III
< 1 MIN READ
DVCon USA 2016: Heralding Formal’s New Wave

DVCon USA 2016: Heralding Formal’s New Wave

March 29, 2016
If you were wondering whether formal verification is becoming a cornerstone of mainstream verification flows, several events at the recent...
By Joe Hupcey III
< 1 MIN READ
Goal posts Aren’t Only for Football – Use Them in Formal Analysis Too!

Goal posts Aren’t Only for Football – Use Them in Formal Analysis Too!

February 1, 2016
With both DVCon and the annual Super Bowl championship football game coming up, one can’t help but think of …...
By Joe Hupcey III
< 1 MIN READ
R2-D2 and Ultra Low Power Design & Verification

R2-D2 and Ultra Low Power Design & Verification

January 19, 2016
[SPOILER ALERT] I suspect virtually all Verification Horizons blog readers have seen Star Wars: The Force Awakens by now, but...
By Joe Hupcey III
< 1 MIN READ
Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

Are You Struggling to Reach Timing Closure with Your Low Power Design – You May Have CDC Problems!

January 7, 2016
First, if you were brought here by a desperate Google search for “timing closure tricks STA RTL” as your tape...
By Joe Hupcey III
< 1 MIN READ
Formal Tech Tip: How Good Properties Can be Over-constrained and How to Fix It

Formal Tech Tip: How Good Properties Can be Over-constrained and How to Fix It

November 18, 2015
Given the dramatic increase in the scalability of formal engines over the past 5 years, “formal testbenches” have grown to...
By Joe Hupcey III
< 1 MIN READ
Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification

Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification

September 22, 2015
Now that summer is over and the kids are settled into their classrooms, it’s a great time for grown-ups to...
By Joe Hupcey III
< 1 MIN READ
How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2

How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2

August 19, 2015
In Part 1 of this series, inspired by security researchers that were able take over a new Jeep and drive...
By Joe Hupcey III
< 1 MIN READ
How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2

How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2

August 5, 2015
[Preface: everywhere it refers to automobiles in this post, you can also swap in “X-Ray machine”, “pacemaker”, and “aircraft”] The...
By Joe Hupcey III
< 1 MIN READ
NEW Formal & CDC Courses on Verification Academy

NEW Formal & CDC Courses on Verification Academy

June 8, 2015
Do you have a really tough verification problem – one that takes seemingly forever for a testbench simulation to solve...
By Joe Hupcey III
< 1 MIN READ
ASYNC 2015: The Most Important CDC Conference You’ve Never Heard Of

ASYNC 2015: The Most Important CDC Conference You’ve Never Heard Of

May 11, 2015
Because Clock Domain Crossing (CDC) verification has been around for well over a decade, it’s tempting to think that CDC...
By Joe Hupcey III
< 1 MIN READ
Do Formal Apps Help D&V Engineers Cross the Chasm Into Direct Formal Property Checking? This Oracle Case Study Suggests They Do (Part 2 of 2)

Do Formal Apps Help D&V Engineers Cross the Chasm Into Direct Formal Property Checking? This Oracle Case Study Suggests They Do (Part 2 of 2)

April 16, 2015
Do automated formal apps really help D&V engineers “cross the chasm” and start using formal verification directly? In Part 1...
By Joe Hupcey III
< 1 MIN READ
Do Formal Apps Help D&V Engineers Cross the Chasm Into Direct Formal Property Checking? This Oracle Case Study Suggests They Do (Part 1 of 2)

Do Formal Apps Help D&V Engineers Cross the Chasm Into Direct Formal Property Checking? This Oracle Case Study Suggests They Do (Part 1 of 2)

April 9, 2015
One of the biggest developments in the formal verification world in the past several years has been the industry-wide growth...
By Joe Hupcey III
< 1 MIN READ
3 Notable Formal-Related Conference Papers of 2014

3 Notable Formal-Related Conference Papers of 2014

January 6, 2015
2014 was an exciting year for formal verification to say the least, and below I call out a sampling of...
By Joe Hupcey III
< 1 MIN READ
ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

ARM® Techcon Paper Report: How Microsoft Saved 4 Man-Months Meeting Their Coverage Closure Goals Using Automated Verification Management & Formal Apps

November 17, 2014
Few verification tasks are more challenging than trying to achieve code coverage goals for a complex system that, by design,...
By Joe Hupcey III
< 1 MIN READ