DVConUS Edition of Verification Horizons is Out!

Hi Everyone,

Hello from those of us willing to brave the Coronavirus to be here at DVConUS. I am pleased to announce the the March, 2020 issue of Verification Horizons is now available. In addition to a discussion about the future of New England Patriots quarterback Tom Brady, you’ll find a wealth of practical verification information in the great collection of articles in this edition:

  • Verify Thy Verifyer, from Verifworks – an overview of some useful UVM tricks and pitfalls to avoid, but the article also introduces their automated rule checker that helps identify strengths and weaknesses in your UVM code.
  • AI-Based Sequence Detection from Agnisys – A fascinating overview of AI for natural language processing, and an introduction to their tool that will auto-generate assertions and sequences from requirements written in a natural language.
  • Using Questa® SLEC to Speed Up Verification of Multiple HDL Outputs from Codasip – a case study of how they use Questa® Sequential Logic Equivalence Checker (SLEC) to compare multiple implementations of a given processor to a fully-verified implementation, reducing many hours of verification down to just minutes.
  • An Open Data Management Tool for Design and Verification from Arastu Systems – a discussion discussion of the requirements for a tool that will allow effective management of Big Data for our verification.
  • Detecting Scurity Vulnerabilities in a RISC-V® Based System-on-Chip from Tortuga Logic – a case study of their experience in winning last year’s Hack@DAC contest by successfully detecting and reporting security bugs in an RTL RISC-V® based SoC.
  • Formal Verification of RISC-V Processors from Axiomise – a good overview of common architectural issues you’ll encounter with RISC-V, and how a formal tool like Questa PropCheck can be used to detect these kinds of bugs early in the design cycle.

If you’re at DVConUS this week, please stop by for an elbow-bump, or just wave.

Leave a Reply