DVCon India: A Smashing Hit!
DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a Design & Verification track to its popular system-level design (ESL) track that has been popular for many years. The main stage played host to the keynote presentations, opening ceremonies and best paper and poster awards.
Several DVCon India keynote presentations, which I will go into more depth later touched on emerging use of virtual platforms in system design and the growing impact India has on design verification. In particular, Mentor’s CEO, Wally Rhines contrasted Wilson Research survey data on design verification from India and the rest of the world. A strong adoption of SystemVerilog and its popular methodology, the Universal Verification Methodology (UVM) was clear from the survey results Wally shared.
But even beyond SystemVerilog and UVM, the discuss of what could come next anchored the first day of DVCon India discussion on Accellera’s exploration of “portable stimulus.” Accellera has a group exploring if the industry is ready to start a standards project on this concept. And the first day when DVCon India attendees were offered an opportunity to learn about this, the multi-company (Mentor Graphics, Breker & CVC) tutorial on the topic was standing room only.
DVCon Europe – The Stage is Set!
A tutorial slot at DVCon Europe will be devoted to the same topic that was popular at DVCon India. For DVCon Europe attendees, you will find Tutorial T9, “Creating Portable Tests with a Graph-Based Test Specification” will cover this topic. Technical representatives from Mentor Graphics and Breker will cover aspects of portable stimulus and offer examples of how it can work. And early application of the technology will be covered by a representative from IBM. To cover the topic appropriately, we have modified the presenters listed in the official printed program and full details are available online. The presenters will be, in this order:
- Holger Horbach, IBM, Germany
- Frederic Krampac, Breker, France
- Staffan Berg, Mentor Graphics, Sweden
Please join us for this tutorial and ensuing conversation and discussion. Verification productivity is a pressing issue and our ability to better control and create stimulus is a step in the direction to address the verification challenges we all face.
One last note, the concept of “portable stimulus” is language agnostic so no matter which language you use for design and verification, the intention is this technology will be able to help. The tutorial will help you understand how using a graph-based approach enables the highest degree of verification re-use, from IP block to sub-system to full-system level verification. You will see how it supports verification in SystemVerilog, Verilog, VHDL, C, C/C++, assembly, and even other non-traditional base languages. And it also can be extended from simulation to emulation to FPGA prototyping, and even silicon validation.
I look forward to seeing you at DVCon Europe in Munich! And if you have not yet registered, please do so to secure your seat.
