Thought Leadership

Better Late Than Never: Magical Verification Horizons DAC Edition

By Tom Fitzpatrick

As some of you may have seen, we release a great DAC edition of Verification Horizons back in June. Unfortunately, we were so focused on preparing for a great Verification Academy Booth at DACBoothPic
that I completely forgot to blog about the issue! Well, as the saying goes, “better late than never.”  In particular, I’d like to call your attention to two articles.

The first is “Best Practices for FPGA and ASIC Development” by my Mentor colleagues Josh Rensch and John Boone, in which they take you through the four development phases of an FPGA project. By separating the process into distinct PLAN, EXECUTE, VERIFY and SUPPORT phases, Josh and John help you establish a manageable process that you can apply to your next project. The key is to identify the techniques, or specific activities, that will be used at each phase, and establish a rigorous set of deliverables for each phase. Just like clear interface specs are necessary for two design blocks to be able to talk to each other, clear deliverables at each phase of the process let different groups work together efficiently to create a robust and well-verified design.

The other article I wanted to point out to you is “Merging SystemVerilog Covergroups by Example” by our friend Eldon Nelson, a verification engineer at Micron Technology. This article explores the options available when defining and using covergroups, establishing some important guidelines that will help you get the most useful information when multiple instances of covergroups are merged together. Be sure to check it out.

The other articles in the issue are:

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This article first appeared on the Siemens Digital Industries Software blog at