This blog is a continuation of a series of blogs, which presents the highlights from the 2010 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on embedded processors, power management, and clock domains. In this blog, I focus on design and verification reuse trends. As I mentioned in my prologue blog to this series (click here), one interesting trend that emerged from the study is that reuse adoption is increasing.
Design Composition Trends
Figure 1 shows the median design composition trends, which compares the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green).
Notice that new logic development has decreased by 34 percent in the last three years, while external IP adoption has increased by 69 percent. This increase in adoption has been driven by IP demand required for SoC development, such as embedded processor cores (e.g., ARM cores) and standard interface cores (e.g., USB cores).
Figure 1. Median design composition trends
Verification Testbench Composition Trends
Figure 2 shows the median testbench composition trends, which compares the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green).
Notice that new verification code development has decreased by 24 percent in the last three years, while external verification IP adoption has increased by 138 percent. This increase has been driven by the emergence of standard on-chip and off-chip bus architectures.
Figure 2. Median testbench composition trends
In my next blog (click here), I’ll shift my focus from design trends to project resource trends. I’ll also present our findings on the project effort spent in verification.