Blog #7 in a 12-part series covering the Digital Twin Best Practices in Electronics Manufacturing mini-webinar series by Jay Gorajia
It’s a constant tension: manufacturers try to reduce costs while maintaining a required level of quality.
Let’s face it – design and manufacturing defects are inevitable in electronics manufacturing. So in order to maintain profitability, we need to “shift left” – that is, to make sure that faults are discovered in as early a stage as possible.
Unfortunately, many of these faults are discovered late in the manufacturing process: only in the product verification phase, during which functional testing is performed. This stage is intended to test functionality alone, and if errors are detected, the task of diagnosis and repair becomes prohibitively expensive, and may even result in missed delivery dates and revenue targets. Boards are more likely to be rejected as scrap – with all the expensive components already placed on them. Many faults could have been detected earlier, in the process verification stage. So why doesn’t this happen?
What’s missing is a comprehensive design-for-testing (DFT) strategy and toolset. Without them, we overlook testing and inspection requirements, and leave it to the functional tests to find process-related faults. The analysis tool should provide a “digital twin” with a rich graphical interface and easy-to-use navigation tools that quickly identify components, nets and test access – in order to position inspection and testing infrastructure in their optimal locations. The digital twin lets companies fully evaluate and review designs early in the NPI life-cycle, thus helping to eliminate surprises when the actual production begins.
In the seventh session of our series of 12 mini-webinars on Implementing “Digital Twin” Best Practices From Design Through Manufacturing we focus on the process engineering stage and discuss how board manufacturers can optimize visual and electrical access in order to facilitate inspection and testing procedures.
Takeaways from the webinar session:
- How Valor® Process Preparation’s DFT solution uses a digital-twin methodology to determine the optimal location for test and inspection infrastructure on the board.
- How the solution proactively “left-shifts” within the design flow to identify issues early in the process – before remediation costs begin to rise.
- How to leverage the ODB++ Process data format to ensure that all the information required to integrate testing and inspection infrastructure is available.