Industry: Semiconductor Devices

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From Functional Monitoring to In-System Test: Extending Voltage-Aware Observability

October 12, 2026

Discover how a Tessent functional monitoring solution, working in conjunction with Movellus Inc. Aeonic Insight™ Droop Detector IP for Power Delivery Network (PDN) telemetry, can provide a multi-instrument monitoring solution that detects a voltage anomaly, and cross-triggers functional monitoring that enables engineers to diagnose issues.

This combined approach provides enhanced visibility and insight, as part of Silicon Lifecycle Management and delivers a more sophisticated approach to monitoring, in order to detect and perform root-cause analysis in-life.

By Tessent Solutions
5 MIN READ
: FPGA demo - RISC-V cores and Droop Detector connected to EA infrastructure.

Detect, diagnose, and debug using sensors and functional monitoring

March 23, 2026

Discover how a Tessent functional monitoring solution, working in conjunction with Movellus Inc. Aeonic Insight™ Droop Detector IP for Power Delivery Network (PDN) telemetry, can provide a multi-instrument monitoring solution that detects a voltage anomaly, and cross-triggers functional monitoring that enables engineers to diagnose issues.

This combined approach provides enhanced visibility and insight, as part of Silicon Lifecycle Management and delivers a more sophisticated approach to monitoring, in order to detect and perform root-cause analysis in-life.

By Tessent Solutions
4 MIN READ
Tessent UltraSight

Beyond the core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight

December 15, 2025

Tessent UltraSight enables system-wide debugging for complex SoCs. A comprehensive solution, it combines embedded hardware IP with powerful host software to provide deep visibility into complex SoCs, supporting the development and optimization of high-performance embedded software.

By Tessent Solutions
3 MIN READ

RISC-V | Solving bus and software deadlock problems in complex SoCs

November 23, 2023

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

By Huw Geddes
2 MIN READ

Debugging RISC-V processors using E-Trace

November 1, 2023

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

By Huw Geddes
3 MIN READ

RISC-V – It’s not just about the core, it’s also about the system

September 28, 2023

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

By Huw Geddes
3 MIN READ
Debugging a RISC-V processor requires integrated hardware and software tools

Debugging a RISC-V processor requires integrated hardware and software tools

September 7, 2023

Tessent Embedded Analytics offers an integrated range of hardware and software tools that accelerate debug of RISC-V based SoCs.

By Huw Geddes
3 MIN READ
Image showing the architecture of a bus-based packetized scan test delivery system. Each core’s DFT can be designed independently and with the most optimal compression configuration.

Video: System-on-chip ATPG with Tessent SSN

June 26, 2023

Learn how Intel adopted Tessent SSN packet-based ATPG and reduced test time by 34% in this video recorded at the 2023 North America U2U symposium.

By Tessent Solutions
< 1 MIN READ

Video: Developing DFT flow for 3D IC at Broadcom

June 26, 2023

Learn how Broadcom used Tessent Multi-die to build a 3D IC flow in this video recorded at the 2023 North America U2U symposium.

By Tessent Solutions
2 MIN READ