Video from DAC: DFT for 2.5D and 3D designs with Tessent Multi-die
At the 2023 Design Automation Conference (DAC), Lee Harrison, the director of automotive solutions for the Tessent group at Siemens EDA, discussed using Tessent Multi-die software to implement DFT on 2.5D and 3D designs.
The presentation was recorded and is now available for anyone to view.
Designing dies for a stacked architecture must incorporate relevant standards so they can be efficiently integrated and packaged. The Tessent Multi-die software enables automation and support for the generation and insertion of hardware that is compliant with the IEEE 1838 standard, defining the IEEE test access architecture for three-dimensional stacked integrated circuits utilizing the IEEE 1687 standard.
Tessent Multi-die utilizes Tessent Streaming Scan Network (SSN) as the optional Flexible Parallel Ports (FPP). The packetized scan data can be streamed through the SSN bus to test just one die at a time or multiple dies at the same time based on specific testing requirements. The SSN bus can also be used to test the interconnect between the dies, just like testing interconnect between hierarchical cores.
Tessent Multi-die can be used to generate and insert an IEEE 1687 IJTAG network that provides access to any IJTAG instrument within the 2.5D or 3D device. By providing the ICL and PDL of an instrument, patterns can be automatically generated and delivered through the die stack to setup or control any IJTAG instrument. Tessent Multi-die integrates well with other Tessent Silicon Lifecycle Solutions products as part of the Tessent Shell flow.
