At the 2020 International Test Conference, a paper by scientists from Siemens Digital Industries Software and Intel, describes how the bus-based scan data distribution architecture solves some of the thorniest problems of testing large complex SoCs.
At the 2020 International Test Conference (ITC), Siemens EDA’s Tessent, with co-authors from Intel, described a packetized data network that optimizes SoC test time and implementation productivity. That author submitted ITC paper is now available for download.
System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods. Test time, planning effort, and physical design closure all become significant challenges. It is harder to drive test of cores concurrently, and core tiling/abutment make balanced pipelining when testing identical cores difficult.
The existing options for optimizing test time fall short. They require analyzing all the cores and subsequently changing the test hardware in the cores. The ability to shift data in and out of the chip are also limited by internal shift speed constraints. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time.
The solution is the Tessent Streaming Scan Network (SSN), a bus-based scan data distribution architecture. It enables simultaneous testing of any number of cores even with few chip I/Os. It reduces test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. SSN provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. The paper also compares the test cost and implementation productivity of SSN with those of Intel’s Structural Test Fabric.
Read the author submitted version of the ITC 2020 technical paper now from Tessent authors Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, and Janusz Rajski, along with Intel scientists Glenn Colon-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant here:
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs