What’s new in Innovator3D IC 2610

The Innovator3D IC 2610 release (available now on Support Center) brings a number of design capabilities and productivity enhancements further enhancing Innovator3D IC Integrators pathfinding and prototyping cockpit that’s suitable for all types of advanced chiplet integration platforms. This release supersedes all previous 2604 releases. Below are the major new capabilities of this release.

Innovator3D IC Integrator

• Full sub-nanometer database resolution
• Unlimited hierarchical floorplans
• Construct device pin array from Lef/Def
• Move linked pins/TSVs as a single object
• Enhanced Property Manager
• Export custom interfaces as a UCIe template for Innovator3D IC Protocol Analyzer
• Large database performance and capacity
• Vertical Daisy Chains support for test vehicles
• 3Dblox 3.0 support for co-design
• Virtual Die Model expansion

Innovator3D IC Layout

• Large database performance and capacity
• Forward Annotate traces and/or via arrays from Innovator3D IC Integrator

Innovator3D IC Integrator

Full sub-nanometer database resolution

The designs datamodel and the full application have been transformed to pico-meter resolution, this was previously supported for 3Dblox file import/export only. Pico-meter support is required to maintain data precision and fidelity when multiple teams on different sub nanometer precision design authoring tools integrate and co-design with Innovator3D IC Integrator.

This capability is available in 2610 as a controlled release – Contact your local Siemens sales or AE to request access

Unlimited hierarchical floorplans

As heterogeneously integrated assemblies scale in complexity, content and size, in order to meet the demand of silicon scaling, designing flat becomes a challenge for the designer to understand the various levels of design data. In 2610 we have introduced unlimited levels of hierarchical device floorplans. This is similar to semiconductor block based design. The designer can now break down the design into multiple floorplans making is easier to manage and comprehend the designs content.

Create device poin/bump array from Lef/Def

If you have a full Lef/Def file, but only need to create a fixed device pin/bump array this capability ignores all the other contents of the Lef/Def file.

Previously the designer would have to create a .csv from the Lef/Def in order to create a device pin array, which is tedious and error prone.

Move stacked and linked pins/TSV’s as a single object

Ability to link device pins together so that they can be moved as a single object retaining their spatial relationships with each other. Pins/TSV’s do not have to be on the same X,Y location. Supports moving stacked pins as a single object. Designer can then move all vertically stacked (and linked TSV) pins for an entire die stack as one object.

Property Manager enhancements

A centralized Property Manager was first introduced in 2604. As Siemens 3D IC central cockpit Innovator3D IC Integrator need to manage a huge numbers of properties on various design objects that get used by downstream analysis and verification tools such as:Calibre nmDRC, Calibre 3DStack, Calibre 3DThermal, Calibre 3DStress, Calibre 3DPERC and the Hyperlynx SI/PI and 3DEM tools

With 2610 it gets more sophisticated management tools such as Property, Value validation, user interface customization, property grouping and filtering. This makes setting up a design for downstream analysis and verification much easier and quicker.

This enables the designer to define, store and supply information for driving early analysis and verification as a consistent single source of data.

Integration with Innovator3D IC Protocol Analyzer

Although Innovator3D IC Protocol Analyzer comes with UCIe standards approved interface templates many designers create modified versions to suit their designs needs, even it they are no longer 100% UCIe standards compliant.  Because of this we now allow customized interfaces to be exported from Innovator3D IC Integrator as a custom template which can then be used for UCIe compliance analysis. Doing this at the pathfinding/prototyping stage allows for interface exploration and prevent downstream issues if a non-compliant interface is used.

Performance and capacity

To meet the ever-insatiable performance, bandwidth and throughput needs of AI, high-performance compute etc silicon scaling continues to accelerate putting more logic chiplets and HBM memory onto a single substrate. This results in an explosion of design size. Innovator3D IC Integrator continues to scale in performance and capacity, in 2610 Innovator3D IC Integrator is enhanced to fully capable of supporting designs of 50 million pins and still provide interactive performance.

Vertical Daisy Chain support

As more devices, interposers and substrates start to be used in stacked configuration the demand for daisy chain test vehicles to consider the stacking which required vertical chain support. In 2610 vertical chains are fully supported including TSVs. A selection of common vertical chain patterns are also provided. The Daisy Chain test vehicle capability is reserved for the 300 product tier of Innovator3D IC Integrator.

3Dblox 3.0 Co-design support

3Dblox versions 2.5 and 3.0 were supported in release 2604. In 2610 Innovator3D IC Integrator now supports Chip-Package Co-design using 3Dblox “common objects”, but we have extended this further to allow the design to map “common objects” to actual design elements such as those shown here.

Enhanced Virtual Die model for Co-design

The Virtual Die Model, or VDM, has been extended in 2510 to support multi metal layer bump macros as these are becoming common and support is required to enable bump macro co-design.

Innovator3D IC Layout

Performance and capacity

Package substrates are also increasing in complexity and size driven by 2.5 and 3D heterogeneously integrated assemblies.  Because of this silicon scaling trend Innovator3D IC Layout has received a number of significant performance and capacity related enhancements in 2610 and has been validated on designs up to 25 million pins and 12 million nets.

Import traces and vias from Innovator3D IC Integrator

Innovator3D IC Layout can now selectively import routed traces and vias, including via arrays and via farms. This is useful as routed traces may be daisy chains that are part of a test vehicle that needs finalizing in Layout, such as adding fiducials etc. They could also come from an imported ODB++ file. Having this capability prevents the Layout user having to recreate these items manually.

For more details on the complete contents of the 2610 release please refer to the release Factsheet and the release notes that are available on Support Center.