Visualizer Debug Environment Webinar Series

Complex testing and methodologies with complex silicon require powerful but simple-to-use debug solutions. In this 3-part web seminar series, debug expert Rich Edelman explains the best debug techniques for UVM, Verilog, and VHDL and demonstrates how you can use the Visualizer Debug Environment to debug and verify your complex SoCs and FPGAs.

Sessions:

Session 1 – Better UVM Debug with Visualizer

  • Tuesday, June 2nd
  • 8:00 AM – 9:00 AM US/Pacific

Session 2 – Introduction to Visualizer for the Verilog Users

  • Tuesday, June 16th
  • 8:00 AM – 9:00 AM US/Pacific

Session 3 – Introduction to Visualizer for the VHDL Users

  • Tuesday, June 30th
  • 8:00 AM – 9:00 AM US/Pacific

Learn more and register.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/news/visualizer-debug-environment-webinar-series/