Corporate

Visualizer Debug Environment Webinar Series

May 12, 2020 • < 1 MIN READ

By Todd Burkholder

Complex testing and methodologies with complex silicon require powerful but simple-to-use debug solutions. In this 3-part web seminar series, debug expert Rich Edelman explains the best debug techniques for UVM, Verilog, and VHDL and demonstrates how you can use the Visualizer Debug Environment to debug and verify your complex SoCs and FPGAs.

Sessions:

Session 1 – Better UVM Debug with Visualizer